-
1.
公开(公告)号:US20250072078A1
公开(公告)日:2025-02-27
申请号:US18940382
申请日:2024-11-07
Applicant: Intel Corporation
Inventor: Andrew W. YEOH , Joseph STEIGERWALD , Jinhong SHIN , Vinay CHIKARMANE , Christopher P. AUTH
IPC: H01L29/66 , H01L21/02 , H01L21/033 , H01L21/28 , H01L21/285 , H01L21/308 , H01L21/311 , H01L21/762 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L23/00 , H01L23/522 , H01L23/528 , H01L23/532 , H01L27/02 , H01L27/088 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/165 , H01L29/167 , H01L29/417 , H01L29/51 , H01L29/78 , H10B10/00
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.
-
2.
公开(公告)号:US20230101723A1
公开(公告)日:2023-03-30
申请号:US18077142
申请日:2022-12-07
Applicant: Intel Corporation
Inventor: Andrew W. YEOH , Joseph STEIGERWALD , Jinhong SHIN , Vinay CHIKARMANE , Christopher P. AUTH
IPC: H01L29/66 , H01L29/78 , H01L27/088 , H01L21/762 , H01L29/06 , H01L21/8234 , H01L21/768 , H01L23/522 , H01L23/532 , H01L29/165 , H01L29/417 , H01L21/033 , H01L21/28 , H01L21/285 , H01L21/308 , H01L21/311 , H01L21/8238 , H01L23/528 , H01L27/092 , H01L27/11 , H01L49/02 , H01L29/08 , H01L29/51 , H01L27/02 , H01L21/02 , H01L29/167
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.
-
公开(公告)号:US20210043627A1
公开(公告)日:2021-02-11
申请号:US17082434
申请日:2020-10-28
Applicant: Intel Corporation
Inventor: Joseph STEIGERWALD , Tahir GHANI , Oleg GOLONZKA
IPC: H01L27/092 , H01L29/417 , H01L27/088 , H01L29/66 , H01L21/768 , H01L23/485 , H01L29/78
Abstract: A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.
-
公开(公告)号:US20230387121A1
公开(公告)日:2023-11-30
申请号:US18232670
申请日:2023-08-10
Applicant: Intel Corporation
Inventor: Joseph STEIGERWALD , Tahir GHANI , Oleg GOLONZKA
IPC: H01L27/092 , H01L27/088 , H01L29/417 , H01L29/66 , H01L21/768 , H01L23/485 , H01L29/78
CPC classification number: H01L27/0924 , H01L27/0886 , H01L29/41791 , H01L29/66795 , H01L29/41766 , H01L21/76897 , H01L23/485 , H01L29/785 , H01L2029/7858 , H01L2924/0002
Abstract: A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.
-
5.
公开(公告)号:US20200044049A1
公开(公告)日:2020-02-06
申请号:US16537020
申请日:2019-08-09
Applicant: Intel Corporation
Inventor: Andrew W. YEOH , Joseph STEIGERWALD , Jinhong SHIN , Vinay CHIKARMANE , Christopher P. AUTH
IPC: H01L29/66 , H01L29/78 , H01L29/167 , H01L27/092 , H01L23/528 , H01L21/8238 , H01L21/768 , H01L21/02 , H01L29/417 , H01L49/02 , H01L27/02 , H01L23/532 , H01L21/285 , H01L29/51 , H01L29/08 , H01L27/11 , H01L21/8234 , H01L21/762 , H01L21/311 , H01L21/308 , H01L21/28 , H01L21/033 , H01L29/06 , H01L29/165 , H01L23/522 , H01L27/088
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.
-
6.
公开(公告)号:US20240047556A1
公开(公告)日:2024-02-08
申请号:US18381442
申请日:2023-10-18
Applicant: Intel Corporation
Inventor: Andrew W. YEOH , Joseph STEIGERWALD , Jinhong SHIN , Vinay CHIKARMANE , Christopher P. AUTH
IPC: H01L29/66 , H10B10/00 , H01L21/02 , H01L21/033 , H01L21/28 , H01L21/285 , H01L21/308 , H01L21/311 , H01L21/762 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L23/522 , H01L23/528 , H01L23/532 , H01L27/02 , H01L27/088 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/165 , H01L29/167 , H01L29/417 , H01L29/51 , H01L29/78
CPC classification number: H01L29/66545 , H10B10/12 , H01L21/02532 , H01L21/02636 , H01L21/0337 , H01L21/28247 , H01L21/28518 , H01L21/28568 , H01L21/3086 , H01L21/31105 , H01L21/31144 , H01L21/76224 , H01L21/76232 , H01L21/76801 , H01L21/76802 , H01L21/76816 , H01L21/76834 , H01L21/76846 , H01L21/76849 , H01L21/76877 , H01L21/76897 , H01L21/823431 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L21/823857 , H01L21/823871 , H01L21/823878 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L23/53209 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L27/0207 , H01L27/0886 , H01L27/0922 , H01L27/0924 , H01L28/20 , H01L28/24 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/41783 , H01L29/41791 , H01L29/516 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/66795 , H01L29/66818 , H01L29/7843 , H01L29/7845 , H01L29/7846 , H01L29/7848 , H01L29/785 , H01L29/7851 , H01L29/7854 , H01L21/02164 , H01L21/0217 , H01L21/0332 , H01L21/76883 , H01L21/76885 , H01L21/823437 , H01L21/823475 , H01L24/16
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.
-
7.
公开(公告)号:US20210066475A1
公开(公告)日:2021-03-04
申请号:US17080694
申请日:2020-10-26
Applicant: Intel Corporation
Inventor: Andrew W. YEOH , Joseph STEIGERWALD , Jinhong SHIN , Vinay CHIKARMANE , Christopher P. AUTH
IPC: H01L29/66 , H01L29/78 , H01L27/088 , H01L21/762 , H01L29/06 , H01L21/8234 , H01L21/768 , H01L23/522 , H01L23/532 , H01L29/165 , H01L29/417 , H01L21/033 , H01L21/28 , H01L21/285 , H01L21/308 , H01L21/311 , H01L21/8238 , H01L23/528 , H01L27/092 , H01L27/11 , H01L49/02 , H01L29/08 , H01L29/51 , H01L27/02 , H01L21/02 , H01L29/167
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.
-
8.
公开(公告)号:US20190164897A1
公开(公告)日:2019-05-30
申请号:US15859416
申请日:2017-12-30
Applicant: Intel Corporation
Inventor: Andrew W. YEOH , Joseph STEIGERWALD , Jinhong SHIN , Vinay CHIKARMANE , Christopher P. AUTH
IPC: H01L23/532 , H01L23/528 , H01L23/522 , H01L21/8234 , H01L27/088
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.
-
-
-
-
-
-
-