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公开(公告)号：US20230122120A1
公开(公告)日：2023-04-20
申请号：US17265549
申请日：2019-08-15
发明人： Shikang Cheng , Yan Gu , Sen Zhang
IPC分类号： H01L27/02 , H01L29/866 , H01L29/66 , H01L29/06
摘要： A transient voltage suppression device includes: a substrate; a first conductive type well region including a first well and a second well; a second conductive type well region including a third well and a fourth well, the third well being disposed between the first well and the second well so as to isolate the first well and the second well, and the second well being disposed between the third well and the fourth well; a zener diode active region; a first doped region, provided in the first well; a second doped region, provided in the first well; a third doped region, provided in the second well; a fourth doped region, provided in the second well; a fifth doped region, provided in the zener diode active region; and a sixth doped region, provided in the zener diode active region.
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公开(公告)号：US11621279B2
公开(公告)日：2023-04-04
申请号：US16425568
申请日：2019-05-29
申请人： ROHM CO., LTD.
发明人： Ryuta Yaginuma
IPC分类号： H01L27/12 , H01L21/762 , H01L23/50 , H01L21/84 , H01L29/866 , H01L29/66
摘要： A semiconductor device includes a semiconductor layer, a transistor cell portion, formed in the semiconductor layer, a first trench, formed in the semiconductor layer, a diode, electrically separated from the transistor cell portion and having a first conductivity type portion and a second conductivity type portion disposed inside the first trench, a second trench, formed in the semiconductor layer, and a bidirectional Zener diode, electrically connected to the transistor cell portion and having a pair of first conductivity type portions, disposed inside the second trench, and at least one second conductivity type portion, formed between the pair of first conductivity type portion.
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公开(公告)号：US20230093961A1
公开(公告)日：2023-03-30
申请号：US17491417
申请日：2021-09-30
IPC分类号： H02H9/04 , H01L27/02 , H01L29/866
摘要： A device includes a protected terminal, a reference terminal, and a rate-triggered circuit coupled to the protected terminal and to the reference terminal. The rate-triggered circuit is configured to provide an output voltage responsive to a ramp rate of a voltage at the protected terminal being greater than a rate threshold. The device also includes a transistor configured to shunt current from the protected terminal to the reference terminal responsive to the rate-triggered circuit output voltage, and a level-sensing circuit configured to turn off the transistor responsive to the voltage at the protected terminal being greater than a level-sense threshold.
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公开(公告)号：US11616179B2
公开(公告)日：2023-03-28
申请号：US17513254
申请日：2021-10-28
申请人： NICHIA CORPORATION
发明人： Kenji Ozeki , Atsushi Kojima , Chinami Nakai
摘要： A method of manufacturing a light emitting device that comprises a first cover member and a second cover member, includes: providing a package that comprises a substrate, a plurality of resin walls, and a recessed part defined by an upper surface of the substrate and lateral surfaces of the plurality of resin walls, wherein the substrate includes a grooved part surrounding a first region; mounting a light emitting element in the first region; forming the second cover member in a region between the lateral surfaces defining the recessed part to an upper edge of an outer perimeter of the grooved part; forming the first cover member, which comprises depositing an uncured resin on the second cover member, and allowing the uncured resin to flow into a groove of the grooved part; and forming a light transmitting member on the first cover member and the light emitting element.
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公开(公告)号：US11532610B2
公开(公告)日：2022-12-20
申请号：US16910598
申请日：2020-06-24
发明人： Yu-Shu Shen
IPC分类号： H01L27/02 , H01L29/866 , H02H9/04
摘要： An Electrostatic Discharge protection circuit with low parasitic capacitance is provided, comprising a first bipolar junction transistor and a first ESD power clamp device. The first bipolar junction transistor is an NPN type of bipolar junction transistor, including a base and an emitter commonly connected to an I/O terminal and a collector connected with the first ESD power clamp device. The first ESD power clamp device is further connected to ground, and can be a Zener diode, PNP type, NPN type of bipolar junction transistor or the like. When a positive ESD pulse is injected, an ESD protection path is consisting of the first bipolar junction transistor and the first ESD power clamp device. When a negative ESD pulse is injected, the ESD protection path is consisting of a parasitic silicon controlled rectifier, thereby reducing parasitic capacitance effectively.
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公开(公告)号：US11508647B2
公开(公告)日：2022-11-22
申请号：US17197107
申请日：2021-03-10
发明人： Toru Sugiyama , Akira Yoshioka , Hung Hung , Yasuhiro Isobe , Hitoshi Kobayashi , Tetsuya Ohno , Naonori Hosokawa , Masaaki Onomura , Masaaki Iwai
IPC分类号： H01L23/52 , H01L23/495 , H01L29/778 , H01L49/02 , H01L29/866
摘要： A semiconductor device includes a semiconductor package including an n-type channel normally-off transistor, a normally-on transistor, a first diode, and a Zener diode; a first terminal provided on the semiconductor package; a plurality of second terminals provided on the semiconductor package, and the second terminals being lined up in a first direction; a third terminal provided on the semiconductor package; a plurality of fourth terminals provided on the semiconductor package; and a plurality of fifth terminals provided on the semiconductor package, and the fifth terminals being lined up in the first direction.
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公开(公告)号：US11444455B2
公开(公告)日：2022-09-13
申请号：US16873112
申请日：2020-02-03
申请人： Eugene Robert Worley
发明人： Eugene Robert Worley
IPC分类号： H02H9/04 , H01L27/02 , H01L29/8605 , H01L29/866
摘要： In certain aspects of the disclosure, a protection circuit includes a first input/output (I/O) pin, a second I/O pad, a shunt clamp coupled to the first I/O pad, and a resistor coupled between the shunt clamp and the second I/O pad. The resistor has a first dynamic resistance at a voltage of 100 millivolts across the resistor, the resistor has a second dynamic resistance at a voltage of three volts across the resistor, and the second dynamic resistance is at least five times greater than the first dynamic resistance.
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公开(公告)号：US11430780B2
公开(公告)日：2022-08-30
申请号：US17266134
申请日：2019-11-01
发明人： Shikang Cheng , Yan Gu , Sen Zhang
IPC分类号： H01L27/02 , H01L21/266 , H01L29/06 , H01L29/74 , H01L29/866
摘要： A TVS device and a manufacturing method therefor. The TVS device comprises: a first doping type semiconductor substrate (100); a second doping type deep well I (101), a second doping type deep well II (102), and a first doping type deep well (103) provided on the semiconductor substrate; a second doping type heavily doped region I (104) provided in the second doping type deep well I (101); a first doping type well region (105) and a first doping type heavily doped region I (106) provided in the second doping type deep well II (102); a first doping type heavily doped region II (107) and a second doping type heavily doped region II (108) provided in the first doping type deep well (105); a second doping type heavily doped region III (109) located in the first doping type well region (105) and the second doping type deep well II (102); and a first doping type doped region (110) provided in the first doping type well region (105).
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公开(公告)号：US11322584B2
公开(公告)日：2022-05-03
申请号：US17066743
申请日：2020-10-09
申请人： DENSO CORPORATION
IPC分类号： H01L29/06 , H01L29/66 , H01L29/866 , H01L21/225 , H01L21/265
摘要： A semiconductor device includes a semiconductor substrate, an upper diffusion region and a lower diffusion region. The semiconductor substrate has a main surface. The upper diffusion region of a first conductivity type is disposed close to the main surface of the semiconductor device. The lower diffusion region of a second conductivity type is disposed up to a position deeper than the upper diffusion region in a depth direction of the semiconductor substrate from the main surface as a reference, and has a higher impurity concentration than the semiconductor substrate. A diode device is provided by having a PN junction surface at an interface between the upper diffusion region and the lower diffusion region, and the PN junction surface has a curved surface disposed at a portion opposite to the main surface.
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公开(公告)号：US20220069184A1
公开(公告)日：2022-03-03
申请号：US17414503
申请日：2020-01-31
申请人： SL VIONICS CO., LTD.
发明人： Kyoung Min KIM , Gye Oul JEONG , Eun Hyun PARK
IPC分类号： H01L33/62 , H01L25/075 , H01L25/16 , H01L29/866 , H01L33/54 , H01L33/00
摘要： Disclosed is a semiconductor light emitting device comprising at least one semiconductor light emitting chip, with each chip including a plurality of electrodes; a plurality of pads arranged at a designated distance from the plurality of electrodes on a plane, respectively; electrical connections provided on the same plane as the plurality of pads for electrically connecting the electrodes and the pads, respectively; and an encapsulation member for covering the at least one semiconductor light emitting chip.
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