公开(公告)号：US11804832B2

公开(公告)日：2023-10-31

申请号：US17514785

申请日：2021-10-29

申请人： Micron Technology, Inc.

发明人： Mishal Kumar ,  Wei Lu Chu

IPC分类号： G11C5/00 ,  H03K17/10 ,  H03K17/687 ,  H03K17/732 ,  G11C5/14 ,  H03K17/30

CPC分类号： H03K17/102 ,  G11C5/144 ,  G11C5/148 ,  H03K17/302 ,  H03K17/6871 ,  H03K17/732 ,  H03K2217/0036

摘要： Embodiments herein relate to protection of a standby amplifier of a memory device. Specifically, an input voltage of the standby amplifier may be reduced to decrease an occurrence of damage to the standby amplifier or components thereof. In some embodiments, the input voltage may be reduced using a voltage divider that provides the reduced input voltage to the standby amplifier during a power up operation. Upon completion of the power up operation, the input voltage of the standby amplifier may return to an operating voltage. The reduced input voltage may reduce the occurrence of damage to the standby amplifier by maintaining a gate to drain voltage of one or more transistors of the standby amplifier below a maximum.

公开(公告)号：US20190028099A1

公开(公告)日：2019-01-24

申请号：US15654430

申请日：2017-07-19

申请人： Hamilton Sundstrand Corporation

发明人： Michael A. Wilson ,  Eduardo Ahuactzin Parra

IPC分类号： H03K17/732

摘要： A fast shut-off solenoid circuit network includes a solenoid circuit and a current dissipation circuit. The solenoid circuit is operable in response to an electrical current, and configured to operate in an enable mode and a disable mode. The current dissipation circuit is configured to dissipate the current discharged from the solenoid circuit in response to invoking the disable mode. The fast shut-off solenoid circuit network further includes a dissipation bypass circuit. The dissipation bypass circuit is configured to divert the current discharged by the solenoid circuit away from current dissipation circuit when operating in the enable mode.

公开(公告)号：US09124272B2

公开(公告)日：2015-09-01

申请号：US14327026

申请日：2014-07-09

申请人： Renesas Electronics Corporation

发明人： Ikuo Fukami

IPC分类号： H03K3/00 ,  H03K17/73 ,  H03K17/16 ,  H03K17/732

CPC分类号： H03K17/08104 ,  H01L27/088 ,  H01L27/0883 ,  H02M3/07 ,  H02P7/28 ,  H03K17/063 ,  H03K17/162 ,  H03K17/168 ,  H03K17/687 ,  H03K17/731 ,  H03K17/732 ,  H03K2217/0018 ,  H03K2217/0081

摘要： An output MOS transistor has a drain connected with a power supply and a source connected with an output terminal. The short-circuit MOS transistor has a source connected with the output terminal. The short-circuit MOS transistor is formed in a semiconductor substrate connected with the power supply. A switching device is formed in a semiconductor region which is formed in the semiconductor substrate, and contains a first diffusion layer connected with the gate of the output MOS transistor and a second diffusion layer formed in the semiconductor region and connected with the drain of the short-circuit MOS transistor.

摘要翻译： 输出MOS晶体管具有与电源连接的漏极和与输出端子连接的源极。 短路MOS晶体管具有与输出端子连接的源极。 短路MOS晶体管形成在与电源连接的半导体衬底中。 开关器件形成在形成在半导体衬底中的半导体区域中，并且包含与输出MOS晶体管的栅极连接的第一扩散层和形成在半导体区域中并与短路的漏极连接的第二扩散层 电路MOS晶体管。

公开(公告)号：US20140091855A1

公开(公告)日：2014-04-03

申请号：US14035598

申请日：2013-09-24

申请人： Pakal Technologies, LLC

发明人： Richard A Blanchard ,  Hidenori Akiyama ,  Woytek Tworzydlo

IPC分类号： H01L29/745 ,  H03K17/732

CPC分类号： H01L29/7455 ,  H01L29/0619 ,  H01L29/0834 ,  H01L29/402 ,  H01L29/7397 ,  H03K17/732

摘要： An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n− layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. Some of the gate regions are first gate regions that only extend into the p-well, and other ones of the gate regions are second gate regions that extend through the p-well and into the n− layer to create a vertical conducting channel when biased. The second gate regions increase the beta of the PNP transistor. When the first gate regions are biased, the base of the NPN transistor is narrowed to increase its beta. When the product of the betas exceeds one, controlled latch-up of the thyristor is initiated. The distributed second gate regions lower the minimum gate voltage needed to turn on the thyristor.

摘要翻译： 绝缘栅极截止晶闸管具有分层结构，其包括形成在p阱中的p +层（例如，衬底），n层，p阱，垂直绝缘栅极区域和栅极区域之间的n +区域 ，从而形成垂直NPN和PNP晶体管。 栅极区域中的一些是仅延伸到p阱中的第一栅极区域，栅极区域中的其他栅极区域是延伸穿过p阱并进入n-层的第二栅极区域，以在偏置时产生垂直导电沟道 。 第二栅极区域增加了PNP晶体管的β。 当第一栅极区域偏置时，NPN晶体管的基极变窄以增加其β。 当betas的乘积超过1时，开始控制闸流闸。 分布式第二栅极区域降低了导通晶闸管所需的最小栅极电压。

公开(公告)号：US5237225A

公开(公告)日：1993-08-17

申请号：US800239

申请日：1991-11-29

申请人： Horst Gruning

发明人： Horst Gruning

IPC分类号： H02M1/06 ,  H03K17/04 ,  H03K17/0814 ,  H03K17/732

CPC分类号： H03K17/732 ,  H03K17/0403 ,  H03K17/08144

摘要： A switching arrangement for an RF-GTO is specified. It comprises a latching-type semiconductor component (GTO) of familiar construction. The circuit for turning off the semiconductor component (GTO) is designed in such a manner that the turn-off gain I.sub.A /I.sub.G, peak is distinctly less than 3 and, in particular, less than or equal to 1. During the turning-off, the drive is hard, that is to say has a high rate of increase dI.sub.G /dt and high current. A capacitance (C.sub.p) is connected directly in parallel with the semiconductor component (GTO).

摘要翻译： 规定了RF-GTO的切换装置。 它包括熟悉的结构的闭锁型半导体部件（GTO）。 用于关断半导体元件（GTO）的电路被设计成使得关断增益IA / IG，峰值明显小于3，特别是小于或等于1.在关断期间 ，驱动力很强，也就是说具有很高的dIG / dt和高电流。 电容（Cp）直接与半导体元件（GTO）并联连接。

公开(公告)号：US5132767A

公开(公告)日：1992-07-21

申请号：US701002

申请日：1991-05-13

申请人： Tsuneo Ogura ,  Katsuhiko Takigami ,  Akio Nakagama ,  Tomokazu Domon

发明人： Tsuneo Ogura ,  Katsuhiko Takigami ,  Akio Nakagama ,  Tomokazu Domon

IPC分类号： H01L29/08 ,  H01L29/744 ,  H03K17/00 ,  H03K17/732

CPC分类号： H01L29/0834 ,  H01L29/744 ,  H03K17/732 ,  H03K2217/0036

摘要： There is disclosed a double gate GTO thyristor having a high gate gain and a high gate sensitivity, and capable of high speed turn-off. The double gate GTO thyristor comprises an anode/emitter layer, first and second base layers and cathode/emitter layer. A semiconductor layer having a conductivity type opposite to that of the anode/emitter layer is formed in the anode/emitter layer and located at a surface portion of the anode/emitter layer. A first gate electrode is connected to the first base layer, and a second gate electrode to the second base layer. An anode electrode is connected to the anode/emitter layer and all the surface of the semiconductor layer. A cathode electrode is connected to the cathode/emitter layer.

摘要翻译： 公开了具有高栅极增益和高栅极灵敏度并且能够高速关断的双栅极GTO晶闸管。 双栅极GTO晶闸管包括阳极/发射极层，第一和第二基极层以及阴极/发射极层。 在阳极/发射极层中形成具有与阳极/发射极层相反的导电类型的半导体层，并且位于阳极/发射极层的表面部分。 第一栅电极连接到第一基极层，第二栅电极连接到第二基极层。 阳极电极连接到阳极/发射极层和半导体层的所有表面。 阴极电极连接到阴极/发射极层。

公开(公告)号：US5077487A

公开(公告)日：1991-12-31

申请号：US575312

申请日：1990-08-30

申请人： Katsuji Iida

发明人： Katsuji Iida

IPC分类号： H03K17/73 ,  H02M1/06 ,  H02M1/08 ,  H03K17/04 ,  H03K17/0412 ,  H03K17/732

CPC分类号： H03K17/0403 ,  H03K17/04126

摘要： A driver circuit for a large capacity switching element like power transistors etc. having an overdrive function. The driver circuit supplies a sharp overdrive current only at the build-up time and the control thereafter is effected by a constant current source so that the current limiting resistor can be saved and the current capacity of the various elements may be decreased.

公开(公告)号：US4833587A

公开(公告)日：1989-05-23

申请号：US171383

申请日：1988-03-21

申请人： Shigeru Sugayama ,  Tadaaki Kariya ,  Tatsuo Shimura ,  Sigeo Tomita

发明人： Shigeru Sugayama ,  Tadaaki Kariya ,  Tatsuo Shimura ,  Sigeo Tomita

IPC分类号： H01L27/06 ,  H03K17/72 ,  H03K17/732

CPC分类号： H01L27/0641 ,  H03K17/72 ,  H03K17/732 ,  H01L2924/0002

摘要： A fraction of current passing through the P-emitter region and N-base region of a thyristor is by-passed to the base-emitter junction of a PNP transistor. The amount of the base current is dependent on the thyristor current. Thus, as the anode current of the thyristor increases, the base current and hence the collector current of the PNP transistor increases. The collector current by-passed to the PNP transistor is fed, via a switch which is closed during the off-time of the thyistor, to the base-collector path of an NPN transistor whose collector and emitter are respectively connected to the gate and cathode of the thyristor. The turn-on voltage across the collector and emitter of the NPN transistor accordingly becomes lower than the gate-cathode voltage of the thyristor. The base-emitter current of the NPN transistor equals the collector current of the PNP transistor, the collector current being a fraction of the anode current by-passed to the PNP transistor. A fraction of the anode current of the turned-on thyristor is utilized as the control power for driving the NPN transistor so that additional external power for turning off the thyristor becomes almost unnecessary.

摘要翻译： 通过晶闸管的P发射极区域和N基极区域的电流的一部分被旁路到PNP晶体管的基极 - 发射极结。 基极电流的量取决于晶闸管电流。 因此，随着晶闸管的阳极电流增加，PNP晶体管的基极电流和集电极电流增加。 旁路到PNP晶体管的集电极电流通过在晶体管截止时间期间闭合的开关馈送到集电极和发射极分别连接到栅极和阴极的NPN晶体管的集电极路径 的晶闸管。 因此，NPN晶体管的集电极和发射极两端的导通电压变得低于晶闸管的栅极 - 阴极电压。 NPN晶体管的基极 - 发射极电流等于PNP晶体管的集电极电流，集电极电流是旁路到PNP晶体管的阳极电流的一部分。 导通晶闸管的阳极电流的一部分被用作用于驱动NPN晶体管的控制功率，使得几乎不需要用于关断晶闸管的附加外部电源。

公开(公告)号：US4752705A

公开(公告)日：1988-06-21

申请号：US937917

申请日：1986-12-04

申请人： Yukinori Tsuruta ,  Kazuto Kawakami

发明人： Yukinori Tsuruta ,  Kazuto Kawakami

IPC分类号： H02M1/06 ,  H03K17/732 ,  H03K17/72

CPC分类号： H03K17/732

摘要： An off-gate circuit for a GTO thyristor comprises a power source for supplying current to the circuit at a predetermined voltage, and a switching circuit connected to the power source for supplying off-gate current to the GTO thyristor at least two different current rates.

摘要翻译： 用于GTO晶闸管的非栅极电路包括用于以预定电压向电路提供电流的电源，以及连接到电源的开关电路，用于向GTO晶闸管提供至少两个不同电流速率的截止电流。

公开(公告)号：US4644240A

公开(公告)日：1987-02-17

申请号：US624372

申请日：1984-06-25

申请人： Akira Horie ,  Takashi Tsuboi

发明人： Akira Horie ,  Takashi Tsuboi

IPC分类号： H02M1/06 ,  H02M7/515 ,  H02M7/521 ,  H03K17/0812 ,  H03K17/725 ,  H03K17/732 ,  H03K17/51

CPC分类号： H02M1/06 ,  H02M7/521 ,  H03K17/08124 ,  H03K17/725 ,  H03K17/732

摘要： A reverse-conducting GTO thyristor comprises a gate turn-off thyristor and a diode which are formed on a single semiconductor substrate so as to have a common layer and be connected electrically in an inverse-parallel connection. A power converter is composed of a plurality of pairs of these reverse-conducting GTO thyristors connected in series, each pair of thyristors being controlled so that they are turned on and off in opposite phases. An OFF gate pulse for one of each pair of thyristors continues from a time on or after the generation of an ON gate pulse for the other thyristor to the time when a recovery current flowing through the diode portion of the first thyristor is extinguished. The thus-extended OFF gate pulse functions to prevent any displacement current flowing through the GTO portion of the first thyristor during the recovery time for the diode portion thereof.

摘要翻译： 反向导通GTO晶闸管包括栅极截止晶闸管和二极管，其形成在单个半导体衬底上以具有公共层并且以反并联连接电连接。 功率转换器由串联连接的多对这些反向导通GTO晶闸管组成，每对晶闸管被控制使得它们以相反的相位导通和截止。 对于每对晶闸管中的一个，对于另一个晶闸管的导通栅极脉冲的产生之后的时间，到流过第一晶闸管的二极管部分的恢复电流熄灭的时刻，每对晶闸管中的一个的截止门脉冲持续。 这样延伸的关闭门脉冲用于防止在其二极管部分的恢复时间期间流过第一晶闸管的GTO部分的任何位移电流。