公开(公告)号：US12009818B2

公开(公告)日：2024-06-11

申请号：US17872445

申请日：2022-07-25

申请人： Shanghai Huali Integrated Circuit Corporation

发明人： Pinhan Chen ,  Chenglei Guo

IPC分类号： G11C11/412 ,  H03K19/017 ,  H03K19/0944 ,  H03K19/1776

CPC分类号： H03K19/1776 ,  G11C11/412 ,  H03K19/01721 ,  H03K19/0944

摘要： The present application discloses a dual-port SRAM having two ports. On a layout, pass gates connecting to the two ports are disposed near pull down transistors of corresponding memory nodes. A cell layout structure of the SRAM cell structure is centrosymmetric. In a first subunit layout structure, a pass gate and a first pull down transistor share the same active region, and an active region of the other pull down transistor is disposed between active regions of the first pull down transistor and a first pull up transistor. The present application improves the symmetry of read paths of the two memory nodes from two ports thus the symmetry of read currents, therefore the variation of the electrical performance of PMOS transistors is reduced and the stability of the electrical performance of the PMOS transistors is improved.

公开(公告)号：US20230402452A1

公开(公告)日：2023-12-14

申请号：US18448155

申请日：2023-08-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Po-Zeng KANG ,  Wen-Shen CHOU ,  Yung-Chow PENG

IPC分类号： H01L27/06 ,  G06F30/392 ,  G06F30/3953 ,  H03K19/0944 ,  H01L27/02

CPC分类号： H01L27/0629 ,  G06F30/392 ,  G06F30/3953 ,  H03K19/09441 ,  H01L27/0207 ,  H01L23/5226

摘要： A method of generating an IC layout diagram includes positioning a resistor unit cell in the IC layout diagram, a resistor of the resistor unit cell including a source/drain metal region, positioning a MOS unit cell in the IC layout diagram, overlapping the resistor unit cell with a first via region, overlapping the MOS unit cell with a second via region, overlapping the first and second via regions with a continuous conductive region, and storing the IC layout diagram in a storage device.

公开(公告)号：US20230318598A1

公开(公告)日：2023-10-05

申请号：US17711845

申请日：2022-04-01

申请人： pSemi Corporation

发明人： Robert Mark Englekirk ,  Keith Rampmeier ,  Arpita Moghe Chadha

IPC分类号： H03K17/693 ,  H03K19/17736 ,  H03K19/0944

CPC分类号： H03K17/693 ,  G06F13/4068 ,  H03K19/0944 ,  H03K19/17744

摘要： Circuits and methods for determining the characteristics of swappable pins in a peripheral in a 1-Wire or similar single-conductor system, thereby allowing each one of two pins to be either an I/O pin (connected to an I/O line) or a CAP pin (connected to a storage capacitor). Embodiments may utilize a hybrid buffer circuit that utilizes an effectively bi-directional PFET pull-up device coupled between the swappable pins A and B. Two open-drain NFETs pull-down devices are used, one on either side of the PFET and coupled to a respective pin (A or B), but with only one NFET being selected to be operable based on pin-determination flag signals from the pin detection circuitry. Such a hybrid buffer circuit would consume significantly less IC area than two complete conventional buffers, resulting in less leakage and less yield loss.

公开(公告)号：US11483002B2

公开(公告)日：2022-10-25

申请号：US15440088

申请日：2017-02-23

申请人： General Electric Company

发明人： Yuanfeng Luo ,  Yuefeng Luo ,  Dale Robert Lombardo ,  Steven Robert Hayashi

IPC分类号： H03K19/0944 ,  B23H1/02

摘要： A multi-loop controller component for an electric discharge machining (EDM) system includes a plurality of power loop circuits coupled to an output of a power supply of the EDM system and configured to receive DC electric power from the power supply. Each power loop circuits electrically-isolated from other power loop circuits. The multi-loop controller component also includes a plurality of transistors. Each transistor is coupled to a respective power loop circuit and is configured to switch between an ON state and an OFF state to generate a pulse of the DC electric power through the respective power loop circuit. In addition, the multi-loop controller component has a drive controller coupled to the plurality of transistors. The drive controller is configured to transmit at least one control signal to at least one of the transistors to facilitate switching the transistor between the ON state and the OFF state.

公开(公告)号：US11476847B2

公开(公告)日：2022-10-18

申请号：US17474726

申请日：2021-09-14

申请人： Mitsubishi Electric Corporation

发明人： Jun Fukudome ,  Kazuya Hokazono ,  Mitsutaka Hano

IPC分类号： H03K3/00 ,  H03K3/037 ,  H03K17/06 ,  H03K17/16 ,  H02M1/08 ,  H03K17/687 ,  H03K19/0185 ,  H03K19/0944

摘要： An object of the present disclosure is to provide a semiconductor device drive circuit stably preventing an erroneous operation in accordance with an application of dV/dt. A semiconductor device drive circuit includes: pulse transmission circuits outputting an on-pulse transmission signal and an off-pulse transmission signal based on a level shift on-pulse signal and a level shift off-pulse signal; a dV/dt detection circuit detecting a dV/dt period based on the level shift on-pulse signal and the level shift off-pulse signal; a logic filter circuit which does not change outputs when both the on-pulse transmission signal and the off-pulse transmission signal are input; and a latch circuit outputting a signal synchronized with an output of the logic filter circuit. The pulse transmission circuit includes impedance adjusting parts reducing a signal level of the on-pulse transmission signal and the off-pulse transmission signal during the dV/dt period.

公开(公告)号：US11323114B2

公开(公告)日：2022-05-03

申请号：US17060566

申请日：2020-10-01

申请人： Lear Corporation

发明人： Raúl Ricart ,  Antoni Ferré Fàbregas

IPC分类号： H03K17/687 ,  H03K17/30 ,  H03K19/0944 ,  B60R21/01

摘要： An electrical system may include a mounting surface, a component configured for connection with the mounting surface and configured to move relative to the mounting surface, and/or an orientation sensor configured to determining an orientation of the component relative to the mounting surface. The orientation sensor may include a first sensor (e.g., a magnetometer, an accelerometer, a gyroscope, etc.) connected, at least indirectly, to the mounting surface, and a second sensor (e.g., a magnetometer, an accelerometer, a gyroscope, etc.) connected to move with the component. The orientation sensor may include an electronic controller. The electronic controller may be configured to compare first information from the first sensor to second information from the second sensor to determine the orientation of the component relative to the mounting surface.

公开(公告)号：US11271569B2

公开(公告)日：2022-03-08

申请号：US17136887

申请日：2020-12-29

申请人： University of Florida Research Foundation, Inc.

发明人： Beomsoo Park ,  Nima Maghari

IPC分类号： H03K19/20 ,  H03K19/0944

摘要： The present disclosure describes systems, apparatuses, and methods for implementing a logic gate circuit structure for operating one or more Boolean functions. Instead of stacking transistors in series to accommodate an increased number of inputs, a parallel configuration is presented that significantly reduces the cascaded number of transistors and the total number of transistors for the same functionality.

公开(公告)号：US20220069821A1

公开(公告)日：2022-03-03

申请号：US17298917

申请日：2019-12-09

申请人： POSTECH Research and Business Development Foundation

发明人： Eun Hwan KIM ,  Jae-Joon KIM

IPC分类号： H03K19/0944

摘要： A pseudo-complementary logic network according to this embodiment includes a first logic stage including a first pull-up circuit of an N-type transistor and a first pull-down circuit and a second logic stage including a second pull-up circuit and a second pull-down circuit of an N-type transistor, wherein an output signal of the second logic stage is provided as an input of the first pull-down circuit, and the first pull-up circuit includes the second pull-down circuit.

公开(公告)号：US11257540B2

公开(公告)日：2022-02-22

申请号：US17067439

申请日：2020-10-09

申请人： GSI Technology, Inc.

发明人： Bob Haig ,  Eli Ehrman ,  Chao-Hung Chang ,  Mu-Hsiang Huang

IPC分类号： G11C11/00 ,  G11C11/419 ,  H03K19/0944 ,  G11C11/418

摘要： A write data processing method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.

公开(公告)号：US11228315B2

公开(公告)日：2022-01-18

申请号：US16947042

申请日：2020-07-15

申请人： Tacho Holdings, LLC

发明人： James John Lupino ,  Tommy Allen Agan

IPC分类号： H03K19/00 ,  H03K19/20 ,  H01L23/52 ,  H01L27/092 ,  H03K19/0944 ,  H01L27/06 ,  H03K19/003 ,  H01L23/522

摘要： Apparatus and associated methods related to a three-dimensional integrated logic circuit that includes a columnar active region. Within the columnar active region resides an interdigitated plurality of semiconductor columns and conductive columns. A plurality of transistors is vertically arranged along each semiconductor column, which extends from a bottom surface of the columnar logic region to a top surface of the columnar logic region. The plurality of transistors are electrically interconnected so as to perform a logic function and to generate a logic output signal at a logic output port in response to a logic input signal received at a logic input port. Each of the plurality of conductive columns is adjacent to at least one of the plurality of semiconductor columns and extends along a columnar axis to one or more interconnection layers at the top and/or bottom surfaces of the columnar active layer.