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公开(公告)号：US20230135657A1
公开(公告)日：2023-05-04
申请号：US18146789
申请日：2022-12-27
摘要： A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.
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公开(公告)号：US11616503B2
公开(公告)日：2023-03-28
申请号：US17742999
申请日：2022-05-12
申请人： PixArt Imaging Inc.
发明人： Swee-Lin Thor , Gim-Eng Chew
摘要： There is provided an optical encoder including a phase shifter circuit, two multiplexers, two digital circuits and four comparators. The phase shifter circuit receives signals from an amplifier and outputs multiple phase shifted signals. Each of the two multiplexers receives a half of the multiple phase shifted signals and outputs two pairs of phase shifted signals, each pair having 180 degrees phase difference, respectively to two comparators connected thereto. Each of the two digital circuits controls the corresponding multiplexer to select the two pairs of phase shifted signals from the half of the multiple phase shifted signals.
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公开(公告)号：US11616502B2
公开(公告)日：2023-03-28
申请号：US17537513
申请日：2021-11-30
申请人： ALi Corporation
发明人： Yi Ting Chen , Ming-Ta Lee
摘要： A phase interpolator capable of preventing a glitch from being generated during a clock signal switching operation and a clock signal selector thereof are provided. The clock signal selector includes a selector and a selection signal generator. The selector receives multiple clock signals with different phases. The selector selects one of the clock signals according to a selection signal to generate a selected clock signal. The selection signal generator is coupled to the selector and generates the selection signal. When the selector switches from selecting a first clock signal to selecting a second clock signal as the selected clock signal, the selection signal generator generates a set time point according to a transition point of one of the first clock signal and the second clock signal whose phase lags behind a phase of the other, and generates the selection signal according to the set time point.
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公开(公告)号：US20230079791A1
公开(公告)日：2023-03-16
申请号：US17904727
申请日：2021-06-23
申请人： ZTE CORPORATION
发明人： Boxiong XU , Tongtong GUAN , Fuqian ZENG
摘要： A clock sending apparatus and method, and a clock receiving apparatus and method are disclosed. The clock sending apparatus may include, an input unit configured to input a first and second input clocks; a sampling unit configured to acquire a first and second sampling clocks, and determine a first frequency control word according to the first and second sampling clocks, the first frequency control word is indicative of a relationship between the first and second sampling clocks, the first sampling clock is determined by the first input clock according to a preset rule, and the second sampling clock is determined by the second input clock according to a preset rule; and a sending unit configured to generate a clock signal according to the first input clock and send the clock signal that carries at least the first frequency control word to a receiving side.
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公开(公告)号：US11606086B2
公开(公告)日：2023-03-14
申请号：US17246839
申请日：2021-05-03
发明人： Bo Liu , Yongduk Lee , Xin Wu
IPC分类号： H02H3/00 , H03K17/082 , H02H1/00 , H03K5/01 , H03K5/00
摘要： A desaturation protection circuit is provided. Aspects includes a main gate driver circuit driving a gate for a switch, a desaturation gate driver circuit coupled to a drain terminal of the switch, a PWM signal supply circuit configured to supply a PWM signal to the desaturation gate driver circuit, and a delay circuit, the delay circuit configured to delay the PWM signal from the PWM signal supply circuit to the desaturation gate driver circuit during a turn-on event for the switch.
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6.发明授权公开(公告)号：US11601116B2
公开(公告)日：2023-03-07
申请号：US17307489
申请日：2021-05-04
摘要： A system for generating a sub-harmonically injection locked phase interpolated output signal. The system comprises ring oscillator (RO) circuitry to generate an output oscillator signal in response to a periodic input signal. The RO circuitry includes a plurality of differential delay RO stages interconnected in cascade within a closed loop, where each RO stage is configured to establish a corresponding delayed version of the output oscillator signal successively shifted in phase by a predetermined phase difference based on a predetermined interpolation mapping scheme. The system further comprises signal injection circuitry coupled to the RO circuitry to apply a first signal having a first input phase and a second signal having a second input phase to the plurality of differential delay RO stages based on the predetermined interpolation mapping scheme to lock a frequency of the output oscillator signal at one half the frequency of the periodic input signal.
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公开(公告)号：US20230067052A1
公开(公告)日：2023-03-02
申请号：US17822375
申请日：2022-08-25
发明人： Lionel Vogt
IPC分类号： H03K5/00
摘要： In an embodiment a radiofrequency doubler includes a first transistor and a second transistor connected in parallel between a first differential output and a first terminal of a current source configured to provide a bias current, a second terminal of the current source being connected to a first supply potential, a third transistor connected between the first terminal of the current source and a second differential output, a circuit configured to apply an AC component of a first differential input and a first DC voltage to a gate of the first transistor, apply an AC component of a second differential input and the first DC voltage to a gate of the second transistor and apply a second DC voltage to a gate of the third transistor, and a feedback loop configured to control the first voltage or the second voltage from a difference between DC components of the first and second differential outputs so as to equalize the DC components.
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公开(公告)号：US11595031B1
公开(公告)日：2023-02-28
申请号：US17457790
申请日：2021-12-06
发明人： Deyi Pi , Gongbao Cheng
IPC分类号： H03K5/1252 , G06F1/08 , H03L7/08 , H03K5/00
摘要： A circuit and a method for eliminating a spurious signal are provided. The circuit includes a phase detector, a spurious estimation and regeneration device, and a phase shifter. After an actual clock signal containing a spurious signal is obtained, the contained spurious signal is estimated based on the reference clock signal that does not contain the spurious signal. Reverse adjustment is performed on the actual clock signal based on the estimated spurious signal to eliminate the spurious signal in the actual clock signal, ensuring eliminating the generated spurious signal by performing reverse adjustment, improving the signal transmission quality, thereby solving the problem of reduced signal quality due to that the spurious signal cannot be suppressed in generation according to the conventional technology.
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公开(公告)号：US11586240B1
公开(公告)日：2023-02-21
申请号：US17867117
申请日：2022-07-18
申请人： Apple Inc.
发明人： Bo Sun , Brian S. Leibowitz , Jafar Savoj , Sanjeev K. Maheshwari
摘要： Embodiments relate to a circuit implementation for controlling a delay of a clock signal. The clock delay control circuit includes a sensing circuit and a phase interpolator controlled by the sensing circuit. The sensing circuit generates a first control signal that increases when a level of a supply voltage increases, and decreases when the level of the supply voltage decreases. Moreover, the sensing circuit generates a second control signal that decreases when the level of the supply voltage increases, and increases when the level of the supply voltage decreases. The phase interpolator includes multiple paths, each having a different propagation delay. The coupling between each path and the output node of the phase interpolator is controlled by the control signals generated by the sensing circuit.
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10.发明授权公开(公告)号：US11560753B2
公开(公告)日：2023-01-24
申请号：US16730004
申请日：2019-12-30
摘要： A motorized shade comprising a motor adapted to lower or raise a shade material for selectively covering an architectural opening based on a position of the sun. The motorized shade comprises a controller adapted to drive the motor phase according to a startup sequence by ramping up amplitude form an initial amplitude to a startup amplitude and ramping up frequency from an initial frequency to a drive frequency, drive the motor phase according to a full drive sequence to move the shade material by driving the motor phase according to a sinusoidal waveform at a set maximum amplitude and at a drive frequency, and drive the motor phase according to a wind down sequence by reducing frequency from the drive frequency to an end frequency and reducing the amplitude from the maximum amplitude to an end amplitude.
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