公开(公告)号：WO0205281A9

公开(公告)日：2002-11-28

申请号：PCT/CA0100949

申请日：2001-06-29

Applicant: MOSAID TECHNOLOGIES INC ,  DEMONE PAUL

Inventor： DEMONE PAUL

IPC: G11C11/401 ,  G11C7/22 ,  G11C8/18 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C7/10

CPC classification number: G11C11/408 ,  G11C7/1039 ,  G11C7/22 ,  G11C8/18 ,  G11C11/405 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4097 ,  G11C2207/2281 ,  G11C2207/229

Abstract: A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.

公开(公告)号：WO0141364A3

公开(公告)日：2001-12-06

申请号：PCT/CA0001420

申请日：2000-11-30

Applicant: MOSAID TECHNOLOGIES INC ,  BROWN DAVID A

Inventor： BROWN DAVID A

IPC: H04L12/56 ,  H04L12/18 ,  H04L12/46 ,  H04L29/06

CPC classification number: H04L12/4641 ,  H04L69/22

Abstract: In a switch including a plurality of ports, an IP Multicast packet arriving on an ingress port a copy of the receiver packet is forwarded to each member of the IP Multicast group at wire-speed. The packet is bridged once to a given egress port and may be routed multiple times out of the egress port. If multiple subnets exist on an egress port, each subnet that requires a copy of the packet will receive the packet with its VLAN ID included in the packet. The received IP Multicast packet for an IP Multicast group is stored in memory, a pointer to the location of the packet in memory is stored for each port to which a copy of the packet is to be forwarded. An IP Multicast forwarding entry is provided for the IP Multicast group. The forwarding entry includes a modification entry for each packet to be forwarded to the IP Multicast group. A copy of the stored packet is modified dependent on the modification entry and forwarded in the next available port cycle for the port.

Abstract translation: 在包括多个端口的交换机中，到达入口端口的IP组播分组接收分组的副本以线速转发给IP组播组的每个成员。 该分组桥接一次到给定的出口端口，并且可以从出口端口多次路由。 如果出口端口上存在多个子网，则需要复制数据包的每个子网将接收包含其VLAN ID的数据包。 接收的IP组播组的IP组播数据包存储在存储器中，存储针对数据包副本要转发到的每个端口的指向存储器中数据包位置的指针。 IP组播组提供IP组播转发表项。 转发条目包括要转发到IP组播组的每个数据包的修改条目。 存储的数据包的副本将根据修改条目进行修改，并在端口的下一个可用端口周期中进行转发。

公开(公告)号：WO2010043032A8

公开(公告)日：2010-07-08

申请号：PCT/CA2009001451

申请日：2009-10-14

Applicant: MOSAID TECHNOLOGIES INC ,  KIM JIN-KI ,  PYEON HONG BEOM

Inventor： KIM JIN-KI ,  PYEON HONG BEOM

IPC: G11C7/10 ,  G11C5/06 ,  G11C7/22 ,  G11C16/06

CPC classification number: G11C7/00 ,  G11C5/02 ,  G11C5/025

Abstract: A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices. The discrete memory devices can be commercial off-the-shelf memory devices or custom memory devices which respond to native, or local memory control signals. The global and local memory control signals include commands and command signals each having different formats. The composite memory device includes a system in package including the semiconductor dies of the discrete memory devices and the bridge device, or can include a printed circuit board having packaged discrete memory devices and a packaged bridge device mounted thereto.

Abstract translation: 一种包括分立存储器装置和桥装置的复合存储器装置，用于响应于具有与存储器装置不兼容的格式或协议的全局存储器控制信号来控制分立存储器装置。 分立存储器设备可以是商用的现成存储器设备或响应于本地或本地存储器控制信号的定制存储器设备。 全局和本地存储器控制信号包括各自具有不同格式的命令和命令信号。 复合存储器件包括包含分立存储器件和桥接器件的半导体管芯的系统级封装，或者可以包括具有封装的分立存储器件和安装在其上的封装桥接器件的印刷电路板。

公开(公告)号：WO2009079772A8

公开(公告)日：2010-01-14

申请号：PCT/CA2008002235

申请日：2008-12-18

Applicant: MOSAID TECHNOLOGIES INC ,  PYEON HONG BEOM

Inventor： PYEON HONG BEOM

IPC: H01L25/065 ,  H01L23/50 ,  H01L23/538

CPC classification number: H01L25/0657 ,  G11C5/02 ,  G11C5/066 ,  G11C16/06 ,  G11C19/00 ,  H01L21/76898 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/00

Abstract: A multi-chip device and method of stacking a plurality substantially identical chips to produce the device are provided. The multi-chip device, or circuit, includes at least one through-chip via providing a parallel connection between signal pads from at least two chips, and at least one through-chip via providing a serial or daisy chain connection between signal pads from at least two chips. Common connection signal pads are arranged symmetrically about a center line of the chip with respect to duplicate common signal pads. Input signal pads are symmetrically disposed about the center line of the chip with respect to corresponding output signal pads. The chips in the stack are alternating flipped versions of the substantially identical chip to provide for this arrangement. At least one serial connection is provided between signal pads of stacked and flipped chips when more than two chips are stacked.

Abstract translation: 提供了堆叠多个基本上相同的芯片以产生该装置的多芯片装置和方法。 多芯片器件或电路包括至少一个穿芯片通孔，其通过提供来自至少两个芯片的信号焊盘之间的并联连接以及至少一个穿芯片通孔，以提供从信号焊盘处的串联或菊花链连接 至少两块芯片。 公共连接信号焊盘相对于重复的公共信号焊盘对称地布置在芯片的中心线上。 输入信号焊盘相对于相应的输出信号焊盘对称地设置在芯片的中心线周围。 堆叠中的芯片是基本上相同的芯片的交替翻转版本，以提供这种布置。 当堆叠超过两个芯片时，至少有一个串行连接提供在堆叠和翻转芯片的信号焊盘之间。

公开(公告)号：WO2008101246A8

公开(公告)日：2009-05-28

申请号：PCT/US2008054307

申请日：2008-02-19

Applicant: MOSAID TECHNOLOGIES INC ,  OH HAKJUNE ,  PRZYBYLSKI STEVEN ,  PYEON HONG BEOM ,  SCHUETZ ROLAND

Inventor： OH HAKJUNE ,  PRZYBYLSKI STEVEN ,  PYEON HONG BEOM ,  SCHUETZ ROLAND

IPC: G11C7/10

CPC classification number: G11C7/1045 ,  G06F13/1678 ,  G11C7/10 ,  Y02D10/14

Abstract: A system having serially connected memory devices in a ring topology organization to realize high speed performance. The memory devices have dynamically configurable data widths such that the system can operate with up to a maximum common number of active data pads to maximize performance, or to operate with a single active data pad to minimize power consumption. Therefore the system can include a mix of memory devices having different data widths. The memory devices are dynamically configurable through the issuance of a single command propagated serially through all the memory devices from the memory controller in a broadcast operation. Robust operation of the system is ensured by implementing a data output inhibit algorithm, which prevents valid data from being provided to the memory controller when read output control signal is received out of its proper sequence.

Abstract translation: 一种在环形拓扑组织中具有串联连接的存储器件以实现高速性能的系统。 存储器件具有动态可配置的数据宽度，使得系统可以以高达最大公共数量的有源数据焊盘操作以最大化性能，或者使用单个有源数据焊盘操作以最小化功耗。 因此，系统可以包括具有不同数据宽度的存储器件的混合。 通过在广播操作中通过从存储器控制器的所有存储器装置串行传播的单个命令的发布来动态地配置存储器件。 通过实现数据输出禁止算法来确保系统的稳健运行，当从其正确的序列中接收到读取输出控制信号时，该算法防止有效数据被提供给存储器控制器。

公开(公告)号：WO2008101246A3

公开(公告)日：2009-02-19

申请号：PCT/US2008054307

申请日：2008-02-19

Applicant: MOSAID TECHNOLOGIES INC ,  PYEON HONG BEOM ,  SCHUETZ ROLAND ,  PRZYBYLSKI STEVEN ,  OH HAKJUNE

Inventor： PYEON HONG BEOM ,  SCHUETZ ROLAND ,  PRZYBYLSKI STEVEN ,  OH HAKJUNE

IPC: G11C7/10

CPC classification number: G11C7/1045 ,  G06F13/1678 ,  G11C7/10 ,  Y02D10/14

Abstract: A system having serially connected memory devices in a ring topology organization to realize high speed performance. The memory devices have dynamically configurable data widths such that the system can operate with up to a maximum common number of active data pads to maximize performance, or to operate with a single active data pad to minimize power consumption. Therefore the system can include a mix of memory devices having different data widths. The memory devices are dynamically configurable through the issuance of a single command propagated serially through all the memory devices from the memory controller in a broadcast operation. Robust operation of the system is ensured by implementing a data output inhibit algorithm, which prevents valid data from being provided to the memory controller when read output control signal is received out of its proper sequence.

Abstract translation: 在环形拓扑结构中串联存储器件以实现高速性能的系统。 存储器设备具有动态可配置的数据宽度，使得系统可以以高达最大数量的活动数据焊盘来操作以最大化性能，或者与单个活动数据焊盘一起操作以最小化功耗。 因此，该系统可以包括具有不同数据宽度的存储器设备的混合。 通过在广播操作中通过从存储器控制器中通过所有存储器设备串行传播的单个命令的发布动态地配置存储器设备。 通过实施数据输出禁止算法来确保系统的稳健操作，该算法防止当读取输出控制信号被接收到其正确序列之外时将有效数据提供给存储器控制器。

公开(公告)号：WO2007036047B1

公开(公告)日：2007-05-24

申请号：PCT/CA2006001606

申请日：2006-09-29

Applicant: MOSAID TECHNOLOGIES INC ,  KIM JIN-KI ,  PYEON HONG BEOM

Inventor： KIM JIN-KI ,  PYEON HONG BEOM

IPC: G11C11/4193 ,  G11C11/4197 ,  G11C16/06

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/4243 ,  G11C5/066 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C2207/107 ,  G11C2216/30

Abstract: An apparatus, system, and method for controlling data transfer between a serial data link interface and memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple serial data links and multiple memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Abstract translation: 公开了一种用于控制半导体存储器中的串行数据链路接口和存储体之间的数据传输的装置，系统和方法。 在一个示例中，公开了具有多个串行数据链路的闪存器件和多个存储器组，其中链路独立于存储体。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。 此外，描述了虚拟多链路配置，其中使用单个链路来模拟多个链路。

公开(公告)号：WO2006081668A1

公开(公告)日：2006-08-10

申请号：PCT/CA2006/000143

申请日：2006-02-03

Applicant: MOSAID TECHNOLOGIES, INC. ,  HAERLE, Dieter ,  MAI, Tony ,  VLASENKO, Peter

Inventor： HAERLE, Dieter ,  MAI, Tony ,  VLASENKO, Peter

IPC: H03K5/135

CPC classification number: H03L7/08 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/095 ,  H03L7/10

Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.

Abstract translation: 延迟锁定环包括初始化电路，其确保将DLL初始化为不接近延迟与控制电压特性的任一端的工作点。 初始化电路强制DLL最初从初始延迟开始搜索锁定点，延迟在一个方向上变化，迫使DLL跳过第一个锁定点。 初始化电路仅允许DLL改变从初始延迟到达到工作点的一个方向的电压控制延迟环的延迟。

公开(公告)号：WO2004003755A2

公开(公告)日：2004-01-08

申请号：PCT/CA0300968

申请日：2003-06-26

Applicant: MOSAID TECHNOLOGIES INC ,  BECCA OSWALD ,  ROTH ALAN ,  MCKENZIE ROBERT

Inventor： BECCA OSWALD ,  ROTH ALAN ,  MCKENZIE ROBERT

IPC: G06F13/18 ,  G06F13/42 ,  G06F17/30 ,  G11C15/00 ,  G06F13/00

CPC classification number: G06F17/30982 ,  G06F13/18 ,  G06F13/4247 ,  G11C15/00

Abstract: A cam system comprising a plurality of CAM devices connected in a serial cascade arrangement, the CAMS in the cascade being connected to an adjacent CAM by a respective forwarding bus, with at most a first CAM in the cascade being connected to a receive data signals from a host controller and at most a last CAM devices being coupled to forward results back to the host controller; and a send signal generation means for supplying a SEND signal to the last CAM; the SEND signal for co-ordinating transfer of the search result from the last CAM to the host controller, the serial cascade arrangement minimising the number of CAMs being connected to a common forwarding bus.

Abstract translation: 一种凸轮系统，包括以串联级联装置连接的多个CAM装置，级联中的CAMS通过相应的转发总线连接到相邻的CAM，其中级联中的至多第一CAM连接到来自 主机控制器和至多最后的CAM设备被耦合以将结果转发回主机控制器; 以及发送信号发生装置，用于向最后一个CAM提供SEND信号; 用于协调将搜索结果从最后一个CAM传送到主机控制器的SEND信号，串行级联布置使得连接到公共转发总线的CAM数量最小化。

公开(公告)号：WO2003065379A1

公开(公告)日：2003-08-07

申请号：PCT/CA2003/000137

申请日：2003-01-30

Applicant: MOSAID TECHNOLOGIES, INC. ,  JIANG, Charles ,  ROTH, Alan

Inventor： JIANG, Charles ,  ROTH, Alan

IPC: G11C15/04

CPC classification number: G06F7/74 ,  G11C15/00

Abstract: A priority encoder circuit for detecting multiple match in a CAM, the priority encoder comprising a plurality of inputs each for receiving a respective matchline signal, the inputs being arranged in a predetermined priority order and being enabled by a matchline signal being received thereon; a plurality of outputs corresponding to ones of said inputs; means for enabling one of the outputs corresponding to an enabled input, that is of the highest priority; and a circuit for logically combining a sufficient number of the inputs and outputs of the PE in order to determine whether more than one respective matchline signals has been received, the determination is based on an observation that for every match line input to the PE, there is a corresponding output from the PE and that the highest priority match should have the match line as well as its corresponding priority match output enabled and that if a match line output is enabled but its corresponding output is not, then there is another higher priority match line output, i.e. there must be multiple match line hits.

Abstract translation: 一种用于在CAM中检测多重匹配的优先编码器电路，所述优先编码器包括多个输入，每个输入用于接收相应的匹配线信号，所述输入以预定的优先级顺序排列，并由其上接收的匹配线信号使能; 对应于所述输入中的一个的多个输出; 用于启用对应于具有最高优先级的使能输入的输出之一的装置; 以及用于逻辑地组合PE的足够数量的输入和输出以便确定是否已经接收到多个相应的匹配线信号的电路，该确定是基于对于输入到PE的每个匹配线的观察，那里 是来自PE的相应输出，并且最高优先级匹配应该具有匹配线以及其对应的优先级匹配输出使能，并且如果匹配线输出被使能但是其对应的输出不是，则存在另一较高优先级匹配 线输出，即必须有多个匹配行命中。