公开(公告)号：WO2005048299A3

公开(公告)日：2005-11-17

申请号：PCT/US2004034810

申请日：2004-10-20

Applicant: FREESCALE SEMICONDUCTOR INC ,  MATHEW LEO ,  MURALIDHAR RAMACHANDRAN

Inventor： MATHEW LEO ,  MURALIDHAR RAMACHANDRAN

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/423 ,  H01L29/788 ,  H01L29/76

CPC classification number: H01L27/108 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10894 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881

Abstract: A transistor (10) is formed having three separately controllable gates (44, 42, 18). The three gate regions may be electrically biased differently and the gate regions may have different conductivity properties. The dielectrics on the channel sidewall may be different than the dielectrics on the top of the channel. Electrical contacts to source, drain and the three gates is selectively made. By including charge storage layers, such as nanoclusters (143, 144), adjacent the transistor channel and controlling the charge storage layers via the three gate regions, both volatile and non-volatile memory cells are realized using the same process to create a universal memory process. When implemented as a volatile cell, the height of the transistor and the characteristics of channel sidewall dielectrics control the memory retention characteristics. When implemented as a nonvolatile cell, the width of the transistor and the characteristics of the overlying channel dielectrics control the memory retention characteristics.

Abstract translation: 晶体管（10）形成有三个可分别控制的栅极（44,42,18）。 三个栅极区域可以被不同地电偏置，并且栅极区域可以具有不同的导电性质。 通道侧壁上的电介质可以不同于通道顶部的电介质。 选择性地制造到源极，漏极和三个栅极的电接触。 通过包括与晶体管沟道相邻的电荷存储层（例如纳米簇（143,144）），并通过三个栅极区域控制电荷存储层，使用相同的工艺来实现易失性和非易失性存储单元，以创建通用存储器 处理。 当实现为易失性单元时，晶体管的高度和通道侧壁电介质的特性控制存储器保持特性。 当被实现为非易失性单元时，晶体管的宽度和上覆通道电介质的特性控制存储器保持特性。

公开(公告)号：WO2004100223A3

公开(公告)日：2005-06-16

申请号：PCT/US2004013377

申请日：2004-04-30

Applicant: FREESCALE SEMICONDUCTOR INC ,  MATHEW LEO ,  RAMACHANDRAN MURALIDHAR ,  MILLER JAMES W

Inventor： MATHEW LEO ,  RAMACHANDRAN MURALIDHAR ,  MILLER JAMES W

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/4763 ,  H01L27/088 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L29/66659 ,  H01L21/26586 ,  H01L21/823468 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7842 ,  Y10S257/90

Abstract: A semiconductor process and resulting transistor includes forming conductive extension spacers (146, 150) on either side of a gate electrode (116). Conductive extensions (146, 150) and gate electrode 116 are independently doped such that each of the structures may be n-type or p-type. Source/drain regions (156) are implanted laterally disposed on either side of the spacers (146, 150). Spacers (146, 150) may be independently doped by using a first angled implant (132) to dope first extension spacer (146) and a second angled implant (140) to dope second spacer (150). In one embodiment, the use of differently doped extension spacers (146, 150) eliminates the need for threshold adjustment channel implants.

Abstract translation: 半导体工艺和所得晶体管包括在栅电极（116）的任一侧上形成导电延伸间隔物（146,150）。 导电延伸部（146,150）和栅电极116被独立地掺杂，使得每个结构可以是n型或p型。 源极/漏极区域（156）被植入在间隔物（146,150）的任一侧上。 间隔物（146,150）可以通过使用第一成角度的植入物（132）来掺杂第一延伸间隔物（146）和第二成角度的植入物（140）以掺杂第二间隔物（150）来独立地掺杂。 在一个实施例中，使用不同掺杂的延伸间隔物（146,150）消除了对阈值调节通道植入物的需要。

公开(公告)号：WO2005048299A2

公开(公告)日：2005-05-26

申请号：PCT/US2004/034810

申请日：2004-10-20

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  MATHEW, Leo ,  MURALIDHAR, Ramachandran

Inventor： MATHEW, Leo ,  MURALIDHAR, Ramachandran

IPC: H01L

CPC classification number: H01L27/108 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10894 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881

Abstract: A transistor (10) is formed having three separately controllable gates (44, 42, 18). The three gate regions may be electrically biased differently and the gate regions may have different conductivity properties. The dielectrics on the channel sidewall may be different than the dielectrics on the top of the channel. Electrical contacts to source, drain and the three gates is selectively made. By including charge storage layers, such as nanoclusters (143, 144), adjacent the transistor channel and controlling the charge storage layers via the three gate regions, both volatile and non-volatile memory cells are realized using the same process to create a universal memory process. When implemented as a volatile cell, the height of the transistor and the characteristics of channel sidewall dielectrics control the memory retention characteristics. When implemented as a nonvolatile cell, the width of the transistor and the characteristics of the overlying channel dielectrics control the memory retention characteristics.

Abstract translation: 晶体管（10）形成为具有三个可单独控制的栅极（44,42,18）。 三个栅极区域可以被不同地电偏置，并且栅极区域可以具有不同的导电性质。 沟道侧壁上的电介质可以不同于沟道顶部上的电介质。 与源极，漏极和三个栅极的电接触是有选择的。 通过在晶体管沟道附近包括诸如纳米团簇（143,144）的电荷存储层并且经由三个栅极区域控制电荷存储层，使用相同的工艺来实现易失性和非易失性存储器单元以创建通用存储器 处理。 当实施为易失性单元时，晶体管的高度和沟道侧壁电介质的特性控制存储器保持特性。 当作为非易失性单元实施时，晶体管的宽度和上面的沟道电介质的特性控制存储器保持特性。

公开(公告)号：WO2006104562A3

公开(公告)日：2008-01-10

申请号：PCT/US2006003528

申请日：2006-02-01

Applicant: FREESCALE SEMICONDUCTOR INC ,  MATHEW LEO ,  KOLAGUNTA VENKAT R ,  SING DAVID C

Inventor： MATHEW LEO ,  KOLAGUNTA VENKAT R ,  SING DAVID C

IPC: H01L21/425 ,  H01L23/58

CPC classification number: H01L29/7835 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/785 ,  H01L29/78624 ,  H01L2924/0002 ,  Y10S438/981 ,  H01L2924/00

Abstract: A method for forming a semiconductor device (10) including forming a semiconductor substrate (12); forming a gate electrode (16) over the semiconductor substrate having a first side and a second side, and forming a gate dielectric under the gate electrode. The gate dielectric has a first area (42) under the gate electrode and adjacent the first side of the gate electrode, a second area (44) under the gate electrode and adjacent the second side of the gate electrode, and a third area (14) under the gate electrode that is between the first area and the second area, wherein the first area is thinner than the second area, and the third area is thinner than the first area and is thinner than the second area.

Abstract translation: 一种形成半导体器件（10）的方法，包括形成半导体衬底（12）; 在所述半导体衬底上形成具有第一侧和第二侧的栅电极，以及在所述栅电极下形成栅电介质。 所述栅极电介质具有位于所述栅电极下方且与所述栅电极的第一侧相邻的第一区域（42），所述栅电极下方的第二区域（44）和所述栅电极的第二侧相邻，以及第三区域 ）在所述第一区域和所述第二区域之间的所述栅极电极下方，其中所述第一区域比所述第二区域薄，并且所述第三区域比所述第一区域薄，并且比所述第二区域薄。

公开(公告)号：WO2007117774A2

公开(公告)日：2007-10-18

申请号：PCT/US2007062557

申请日：2007-02-22

Applicant: FREESCALE SEMICONDUCTOR INC ,  MATHEW LEO ,  MURALIDHAR RAMACHANDRAN ,  DHANDAPANI VEERARAGHAVAN

Inventor： MATHEW LEO ,  MURALIDHAR RAMACHANDRAN ,  DHANDAPANI VEERARAGHAVAN

IPC: H01L21/3205

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L21/28282 ,  H01L29/6653 ,  H01L29/66825 ,  H01L29/66833

Abstract: Removing a portion of a structure in a semiconductor device to separate the structure. The structure has two portions (109, 107) of different heights. In one example, the structure is removed by forming a spacer (203) over the lower portion adjacent to the sidewall of the higher portion. A second material (303) is then formed on the structure outside of the spacer. The spacer is removed and the portion under the spacer is then removed to separate the structure at that location. In one embodiment, separate channel regions are implemented in the separated structures. In other embodiments, separate gate structures are implemented in the separated structures.

Abstract translation: 去除半导体器件中的一部分结构以分离结构。 该结构具有不同高度的两个部分（109,107）。 在一个示例中，通过在与较高部分的侧壁相邻的下部分上形成间隔物（203）来移除结构。 然后在间隔件外部的结构上形成第二材料（303）。 移除间隔物，然后移除间隔物下面的部分以在该位置分离结构。 在一个实施例中，在分离的结构中实现单独的通道区域。 在其他实施例中，在分离的结构中实现单独的门结构。

公开(公告)号：WO2007098305A2

公开(公告)日：2007-08-30

申请号：PCT/US2007/060843

申请日：2007-01-22

Applicant: FREESCALE SEMICONDUCTOR INC. ,  MATHEW, Leo ,  GE, Lixin ,  VEERARAGHAVAN, Surya

Inventor： MATHEW, Leo ,  GE, Lixin ,  VEERARAGHAVAN, Surya

IPC: H01L27/12

CPC classification number: H01L29/78615 ,  H01L29/785

Abstract: A method for making a semiconductor device includes patterning a semiconductor layer (14), overlying an insulator layer (12), to create a first active region (28) and a second active region (30), wherein the first active region is of a different height from the second active region, and wherein at least a portion of the first active region has a first conductivity type and at least a portion of the second active region has a second conductivity type different from the first conductivity type in at least a channel region of the semiconductor device. The method further includes forming a gate structure (26) over at least a portion of the first active region and the second active region. The method further includes removing a portion of the second active region on one side of the semiconductor device.

Abstract translation: 制造半导体器件的方法包括图案化覆盖绝缘体层（12）的半导体层（14），以形成第一有源区（28）和第二有源区（30），其中第一有源区为 与第二有源区不同的高度，并且其中第一有源区的至少一部分具有第一导电类型，并且第二有源区的至少一部分具有与至少一个沟道中的第一导电类型不同的第二导电类型 半导体器件的区域。 该方法还包括在第一有源区域和第二有源区域的至少一部分上形成栅极结构（26）。 该方法还包括去除半导体器件一侧上的第二有源区的一部分。

公开(公告)号：WO2007044190A3

公开(公告)日：2007-04-19

申请号：PCT/US2006/036703

申请日：2006-09-20

Applicant: FREESCALE SEMICONDUCTOR INC. ,  MATHEW, Leo ,  RAO, Rajesh, A. ,  MURALIDHAR, Ramachandran

Inventor： MATHEW, Leo ,  RAO, Rajesh, A. ,  MURALIDHAR, Ramachandran

IPC: H01L21/302

Abstract: A semiconductor device (10) includes a plurality of pillars (22) formed from a conductive material (16). The pillars are formed by using a plurality of nanocrystals (20) as a hardmask for patterning the conductive material (16). A thickness of the conductive material determines the height of the pillars. Likewise, a width of the pillar is determined by the diameter of a nanocrystal (20). In one embodiment, the pillars (22) are formed from polysilicon and function as the charge storage region of a non-volatile memory cell (25) having good charge retention and low voltage operation. In another embodiment, the pillars are formed from a metal and function as a plate electrode for a metal-insulator-metal (MIM) capacitor (50) having an increased capacitance without increasing the surface area of an integrated circuit.

公开(公告)号：WO2007120296A2

公开(公告)日：2007-10-25

申请号：PCT/US2006/061312

申请日：2006-11-29

Applicant: FREESCALE SEMICONDUCTOR INC. ,  MATHEW, Leo ,  KHAZHINSKY, Michael G.

Inventor： MATHEW, Leo ,  KHAZHINSKY, Michael G.

IPC: H01L21/8234

CPC classification number: H01L27/0811 ,  H01L29/0657 ,  H01L29/42312 ,  H01L29/7391 ,  H01L29/785

Abstract: An electronic device (10) can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member (101) spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member (102), spaced apart from and adjacent to the junction, can be both electrically connected to a second signal line and electrically insulated (32, 22) from the first conductive member. The junction diode structure can include a p-n or a p-i-n junction. A process for forming the electronic device is also described.

Abstract translation: 电子设备（10）可以包括门控二极管，其中门控二极管包括包括结的结二极管结构。 与结点隔开并相邻的第一导电构件（101）可以连接到第一信号线。 与结点间隔开并与其相邻的第二导电构件（102）可以电连接到第二信号线并与第一导电构件电绝缘（32,22）。 结二极管结构可以包括p-n或p-i-n结。 还描述了用于形成电子设备的过程。

公开(公告)号：WO2007117774A3

公开(公告)日：2007-10-18

申请号：PCT/US2007/062557

申请日：2007-02-22

Applicant: FREESCALE SEMICONDUCTOR INC. ,  MATHEW, Leo ,  MURALIDHAR, Ramachandran ,  DHANDAPANI, Veeraraghavan

Inventor： MATHEW, Leo ,  MURALIDHAR, Ramachandran ,  DHANDAPANI, Veeraraghavan

IPC: H01L21/00

Abstract: Removing a portion of a structure in a semiconductor device to separate the structure. The structure has two portions (109, 107) of different heights. In one example, the structure is removed by forming a spacer (203) over the lower portion adjacent to the sidewall of the higher portion. A second material (303) is then formed on the structure outside of the spacer. The spacer is removed and the portion under the spacer is then removed to separate the structure at that location. In one embodiment, separate channel regions are implemented in the separated structures. In other embodiments, separate gate structures are implemented in the separated structures.

公开(公告)号：WO2007047164A2

公开(公告)日：2007-04-26

申请号：PCT/US2006/039177

申请日：2006-10-04

Applicant: FREESCALE SEMICONDUCTOR INC. ,  KALPAT, Sriram S. ,  MATHEW, Leo ,  MOOSA, Mohamed S. ,  SADD, Michael A. ,  SANCHEZ, Hector

Inventor： KALPAT, Sriram S. ,  MATHEW, Leo ,  MOOSA, Mohamed S. ,  SADD, Michael A. ,  SANCHEZ, Hector

IPC: H01L29/76 ,  H01L21/336

CPC classification number: H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/0995

Abstract: A voltage controlled oscillator (VCO) (40) has a plurality (42, 44, 46) of series-connected inverters. Within each inverter a first transistor (48) has a first current electrode coupled to a first power supply voltage terminal (VDD), a second current electrode, a first control electrode coupled to an output terminal of another inverter of the plurality of series-connected inverters, and a second control electrode for receiving a first bias signal. A second transistor (50) has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply voltage terminal (VSS), and a first control electrode coupled to the first control electrode of the first transistor. The second control electrode of the first transistor of each inverter receives a same or separate analog control signal (VGP, VPP OR DNP) to adjust the threshold voltage of the first transistors thereof to affect frequency and phase of the VCO's signal.

Abstract translation: 压控振荡器（VCO）（40）具有多个（42,44,46）串联逆变器。 在每个逆变器内，第一晶体管（48）具有耦合到第一电源电压端（VDD）的第一电流电极，第二电流电极，耦合到多个串联连接的另一个反相器的输出端的第一控制电极 逆变器和用于接收第一偏置信号的第二控制电极。 第二晶体管（50）具有耦合到第一晶体管的第二电流电极的第一电流电极，耦合到第二电源电压端子（VSS）的第二电流电极和耦合到第一控制电极的第一控制电极的第一控制电极 第一个晶体管。 每个逆变器的第一晶体管的第二控制电极接收相同或分开的模拟控制信号（VGP，VPP或DNP），以调整其第一晶体管的阈值电压以影响VCO信号的频率和相位。