公开(公告)号：WO2014039565A1

公开(公告)日：2014-03-13

申请号：PCT/US2013/058075

申请日：2013-09-04

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Xia ,  KANG, Seung H.

IPC: H01L23/525 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

CPC classification number: G11C17/02 ,  G11C11/005 ,  G11C11/5607 ,  G11C11/5692 ,  G11C17/00 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/22 ,  H01L27/224 ,  H01L43/08 ,  H01L43/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A one time programmable (OPT) and multiple time programmable (MTP) structure is constructed in a back end of line (BEOL) process using only one, two or three masks. The OTP/MTP structure can be programmed in one of three states, a preprogrammed high resistance state, and a programmable low resistance state and a programmable very high resistance state. In the programmable low resistance state, a barrier layer is broken down during an anti-fuse programming so that the OTP/MTP structure exhibits resistance in the hundred ohm order of magnitude. In the very high resistance state a conductive fuse is blown open during programming so that the OTP/MTP structure exhibits resistance in the mega-ohm order of magnitude. The OTP/MTP structure may include a magnetic tunnel junction (MTJ) structure or a metalinsulator- metal (MIM) capacitor structure.

Abstract translation: 仅使用一个，两个或三个掩模，在后端（BEOL）过程中构造了一次性可编程（OPT）和多时间可编程（MTP）结构。 OTP / MTP结构可以编程为三种状态之一，预编程高电阻状态，可编程低电阻状态和可编程非常高电阻状态。 在可编程低电阻状态下，在抗熔丝编程期间阻挡层被分解，使得OTP / MTP结构呈现出百欧姆量级的电阻。 在非常高的电阻状态下，在编程期间导通熔丝被断开，使得OTP / MTP结构呈现以兆欧姆数量级的电阻。 OTP / MTP结构可以包括磁隧道结（MTJ）结构或金属绝缘体金属（MIM）电容器结构。

公开(公告)号：WO2009042913A1

公开(公告)日：2009-04-02

申请号：PCT/US2008/077943

申请日：2008-09-26

Applicant: SANDISK 3D, LLC ,  HERNER, S., Brad ,  SCHEUERLEIN, Roy, E. ,  PETTI, Christopher, J.

Inventor： HERNER, S., Brad ,  SCHEUERLEIN, Roy, E. ,  PETTI, Christopher, J.

IPC: G11C16/10

CPC classification number: G11C17/16 ,  G11C11/5685 ,  G11C11/5692 ,  G11C13/0007 ,  G11C17/06 ,  G11C17/146 ,  G11C17/165 ,  G11C2213/32 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021

Abstract: Methods are described to fabricate, program, and sense a multilevel one-time- programmable memory cell including a steering element such as a diode and two, three, or more dielectric antifuses in series. The antifuses may be of different thicknesses, or may be formed of dielectric materials having different dielectric constants, or both. The antifuses and programming pulses are selected such that when the cell is programmed, the largest voltage drop in the memory cell is across only one of the antifuses, while the other antifuses allow some leakage current. In some embodiments, the antifuse with the largest voltage drop breaks down, while the other antifuses remain intact. In this way, the antifuses can be broken down individually, so a memory cell having two, three, or more antifuses may achieve any of three, four, or more unique data states.

Abstract translation: 描述了制造，编程和感测多级一次可编程存储器单元的方法，所述存储单元包括诸如二极管和二，三个或更多个串联的电介质反熔丝的转向元件。 反熔丝可以具有不同的厚度，或者可以由具有不同介电常数的介电材料或两者形成。 选择反熔丝和编程脉冲，使得当单元被编程时，存储单元中的最大电压降仅跨越反熔丝中的一个，而另一个反熔丝允许一些漏电流。 在一些实施例中，具有最大电压降的反熔丝分解，而其它反熔丝保持完整。 以这种方式，可以单独地分解反熔丝，因此具有两个，三个或更多个反熔丝的存储单元可以实现三个，四个或更多个唯一数据状态中的任何一个。

公开(公告)号：WO2009002475A1

公开(公告)日：2008-12-31

申请号：PCT/US2008/007800

申请日：2008-06-23

Applicant: SANDISK 3D LLC ,  KUMAR, Tanmay ,  HERNER, S., Brad ,  PETTI, Christopher, J.

Inventor： KUMAR, Tanmay ,  HERNER, S., Brad ,  PETTI, Christopher, J.

IPC: G11C13/00 ,  G11C17/16

CPC classification number: G11C13/00 ,  G11C11/5692 ,  G11C13/0069 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C2013/009 ,  G11C2213/33 ,  H01L27/101

Abstract: A method of operating a nonvolatile memory cell includes providing the nonvolatile memory cell comprising a diode which is fabricated in a first resistivity, unprogrammed state, and applying a forward bias to the diode having a magnitude greater than a minimum voltage required for programming the diode to switch the diode to a second resistivity, programmed state. The second resistivity state is lower than the first resistivity state.

Abstract translation: 一种操作非易失性存储单元的方法包括提供非易失性存储单元，该非易失性存储单元包括以第一电阻率，未编程状态制造的二极管，以及将正向偏压施加到具有大于将二极管编程所需的最小电压的二极管的幅度 将二极管切换到第二电阻率，编程状态。 第二电阻率状态低于第一电阻率状态。

公开(公告)号：WO2007038665A1

公开(公告)日：2007-04-05

申请号：PCT/US2006/037803

申请日：2006-09-27

Applicant: SANDISK 3D LLC ,  KUMAR, Tanmay ,  HERNER, S., Brad

Inventor： KUMAR, Tanmay ,  HERNER, S., Brad

IPC: H01L27/10 ,  H01L27/24 ,  G11C11/56

CPC classification number: G11C11/5692 ,  G11C11/005 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C17/14 ,  G11C2211/5641 ,  G11C2211/5646 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/148

Abstract: A nonvolatile memory cell comprising doped semiconductor material and a diode can store memory states by changing the resistance of the doped semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) Set pulses are of short duration and above a threshold voltage, while reset pulses are longer duration and below a threshold voltage. In some embodiments multiple resistance states can be achieved, allowing for a multi-state cell, while restoring a prior high-resistance state allows for an rewriteable cell. In some embodiments, the diode and a switchable memory formed of doped semiconductor material are formed in series, while in other embodiments, the diode itself serves as the semiconductor switchable memory element.

Abstract translation: 包括掺杂半导体材料和二极管的非易失性存储单元可以通过施加设置脉冲（降低电阻）或复位脉冲（增加电阻）来改变掺杂半导体材料的电阻来存储存储器状态。设置脉冲的持续时间短， 高于阈值电压，而复位脉冲的持续时间更长并低于阈值电压。 在一些实施例中，可以实现多个电阻状态，允许多状态单元，同时恢复先前的高电阻状态允许可重写单元。 在一些实施例中，二极管和由掺杂半导体材料形成的可切换存储器是串联形成的，而在其它实施例中，二极管本身用作半导体可切换存储元件。

公开(公告)号：WO2005078732A1

公开(公告)日：2005-08-25

申请号：PCT/US2005/002833

申请日：2005-02-02

Applicant: IOTA TECHNOLOGY, INC.

Inventor： HO, Iu-Meng, Tom

IPC: G11C11/56

CPC classification number: G11C11/5607 ,  G11C7/1006 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/565 ,  G11C11/5657 ,  G11C11/5678 ,  G11C11/5692 ,  G11C13/0004 ,  G11C16/0483 ,  G11C29/00

Abstract: An electronic memory comprising a memory cell pair with each memory cell capable of existing in three or more electronic memory states so that the pair is capable of existing in nine electronic states. The memory cell is capable of storing three data bits plus an extra state that can be used for data integrity. The memory can be a flash memory, a ROM, a dynamic memory, an OUM, a MRAM, a NAND memory, or a NOR memory.

Abstract translation: 一种电子存储器，包括具有能够以三个或更多个电子存储器状态存在的每个存储器单元的存储器单元对，使得该对能够以九个电子状态存在。 存储单元能够存储三个数据位加上可用于数据完整性的额外状态。 存储器可以是闪速存储器，ROM，动态存储器，OUM，MRAM，NAND存储器或NOR存储器。

公开(公告)号：WO2004090909A1

公开(公告)日：2004-10-21

申请号：PCT/JP1995/002715

申请日：1995-12-27

Applicant: 稲田 暢文 ,  重松 厚ニ ,  北吹 順一 ,  林 哲也

Inventor： 稲田 暢文 ,  重松 厚ニ ,  北吹 順一 ,  林 哲也

IPC: G11C17/12

CPC classification number: G11C11/56 ,  G11C7/06 ,  G11C11/565 ,  G11C11/5692 ,  G11C16/32 ,  G11C2211/5642

Abstract: A mask ROM constituted in such a manner as to read information by utilizing delay time accumulated when a read signal applied to a memory cell connected between a word line WL1 and a bit line BU crossing the word line WL1 passes through delay elements R1 to R7, that is, a mask ROM having a structure for reading out the stored information with consideration for a time axis. The on-off operation of switching transistors T1 to T8 is controlled by the outputs of the delay elements R1 to R7, and the information appearing on the bit line BL1 is serially read out at a predetermined timing corresponding to the time delay of each delay device R1 to R7.

Abstract translation: 当通过施加到连接在字线WL1和与字线WL1之间的位线BU之间的存储单元的读取信号通过延迟元件R1至R7时，利用延迟时间累加的方式构成掩模ROM， 即具有考虑时间轴读出存储的信息的结构的掩模ROM。 开关晶体管T1至T8的导通截止操作由延迟元件R1至R7的输出控制，并且在对应于每个延迟器件的时间延迟的预定定时，串行地读出出现在位线BL1上的信息 R1至R7。

公开(公告)号：WO2004001802A3

公开(公告)日：2004-08-05

申请号：PCT/US0319303

申请日：2003-06-19

Applicant: MICRON TECHNOLOGY INC

Inventor： PRALL KIRK ,  FORBES LEONARD

IPC: H01L21/8247 ,  G11C11/56 ,  G11C16/04 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC classification number: H01L29/7926 ,  G11C11/5692 ,  G11C16/0466 ,  G11C16/0475 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7923

Abstract: An array of memory cells configured to store at least one bit per one F includes substantially vertical structures (34) providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.

Abstract translation: 配置为存储每个F 2至少一个位的存储器单元的阵列包括基本上垂直的结构（34），其提供间隔距离等于阵列的最小间距的一半的距离的电子存储器功能。 提供电子存储器功能的结构被配置为存储每个门多于一个位。 阵列还包括到存储器单元的电接触，包括基本垂直的结构。 电池可以被编程为具有与栅极绝缘体相邻的多个电荷水平中的一个，其邻近于第一源极/漏极区域，使得沟道区域具有第一电压阈值区域（Vt1）和第二电压阈值区域（Vt2） 并且使得编程单元以降低的漏极源电流工作。

公开(公告)号：WO2004003926A2

公开(公告)日：2004-01-08

申请号：PCT/US0320051

申请日：2003-06-25

Applicant: MATRIX SEMICONDUCTOR INC

Inventor： JOHNSON MARK G

IPC: G11C11/56 ,  G11C17/12

CPC classification number: G11C16/0483 ,  G11C11/5692 ,  G11C17/123

Abstract: An integrated circuit includes a serially-connected, multi-level, mask-programmed read-only memory array. The memory cells are preferably programmed using selective ion implantation of at least two threshold-adjusting ion implants during the manufacture of the integrated circuit to store more than one bit of information within each memory cell, which are chosen to generate an evenly spaced set of different transistor threshold voltages.

Abstract translation: 集成电路包括串行连接的多电平掩模编程的只读存储器阵列。 存储器单元优选地在集成电路的制造期间使用选择性离子注入至少两个阈值调节离子注入来存储每个存储器单元内的多于一位的信息，该信息被选择以产生均匀间隔的不同组合 晶体管阈值电压。

公开(公告)号：WO2004001802A2

公开(公告)日：2003-12-31

申请号：PCT/US2003/019303

申请日：2003-06-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： PRALL, Kirk ,  FORBES, Leonard

IPC: H01L

CPC classification number: H01L29/7926 ,  G11C11/5692 ,  G11C16/0466 ,  G11C16/0475 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7923

Abstract: An array of memory cells configured to store at least one bit per one F 2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vtl) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.

Abstract translation: 配置为存储每个F 2至少一个位的存储器单元的阵列包括基本上垂直的结构，提供间隔距离等于阵列的最小间距的一半的距离的电子存储器功能。 提供电子存储器功能的结构被配置为存储每个门多于一个位。 阵列还包括到存储器单元的电接触，包括基本垂直的结构。 电池可以被编程为具有与栅极绝缘体相邻的多个电荷电平中的一个，该栅极绝缘体与第一源极/漏极区相邻，使得沟道区具有第一电压阈值区域（Vt1）和第二电压阈值区域（Vt2） 并且使得编程单元以降低的漏极源电流工作。

公开(公告)号：WO0116999A2

公开(公告)日：2001-03-08

申请号：PCT/US0023503

申请日：2000-08-25

Applicant: MACRONIX AMERICA INC

Inventor： LU TAO CHENG ,  TSAI WEN-JER ,  CHANG YAO WEN ,  WANG MAM TSUNG

IPC: G11C11/56 ,  H01L

CPC classification number: G11C11/5692 ,  G11C11/56

Abstract: A method of providing a multilevel programmed Mask ROM that begins by fabricating an unprogrammed mask ROM. The transistors in the mask ROM array are programmed with one of a plurality of threshold voltages using low concentration ion implantation. The method minimizes the leakage current during reading of the array from at least the transistors programmed with a first level threshold voltage. Minimization of leakage current includes biasing at least the first level threshold voltage programmed transistors by applying a negative voltage to the gates of those transistors, implanting at least standard ion implantation dosages in regions surrounding the first level threshold voltage programmed transistors, or by selecting an inhibiting source voltage that substantially eliminates leakage current from at least the first level threshold voltage programmed transistors and then reading the array by applying the inhibiting source voltage to the sources and the inhibiting source voltage plus approximately 1.2V to the drains of the transistors.

Abstract translation: 一种提供多级编程掩模ROM的方法，该方法从制造未编程的掩模ROM开始。 使用低浓度离子注入用多个阈值电压中的一个对掩模ROM阵列中的晶体管进行编程。 该方法在从至少用第一电平阈值电压编程的晶体管读取阵列期间最小化泄漏电流。 最小化泄漏电流包括通过向这些晶体管的栅极施加负电压，至少在第一级阈值电压编程晶体管周围的区域中注入标准离子注入剂量，或者通过选择抑制 源电压基本上消除至少来自第一电平阈值电压编程的晶体管的泄漏电流，然后通过将抑制源电压施加到源并且将抑制源电压加上大约1.2V加上晶体管的漏极来读取阵列。