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    ELECTRON BARRIER HEIGHT CONTROLLED INTERFACES OF RESISTIVE SWITCHING LAYERS IN RESISTIVE RANDOM ACCESS MEMORY CELLS
    1.
    发明申请
    ELECTRON BARRIER HEIGHT CONTROLLED INTERFACES OF RESISTIVE SWITCHING LAYERS IN RESISTIVE RANDOM ACCESS MEMORY CELLS 审中-公开
    电阻式随机存取存储器电容栅极高度控制电阻开关层的界面

    公开(公告)号：WO2016085665A1

    公开(公告)日：2016-06-02

    申请号：PCT/US2015/060368

    申请日：2015-11-12

    Applicant: INTERMOLECULAR, INC.

    Inventor： WANG, Yun ,  NARDI, Federico

    IPC: H01L29/51

    CPC classification number: H01L45/12 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1625

    Abstract: Provided are resistive switching memory cells and method of forming such cells. A memory cell includes a resistive switching layer disposed between two buffer layers. The electron barrier height of the material used for each buffer layer is less than the electron barrier height of the material used for the resistive switching layer. Furthermore, the thickness of each buffer layer may be less than the thickness of the resistive switching layer. The buffer layers reduce diffusion between the resistive switching layer and electrodes. Furthermore, the buffer layers improve data retention and prevent unintentional resistive switching when a reading signal is applied to the memory cell. The reading signal uses a low voltage and most of the electron tunneling is blocked by the buffer layers during this operation. On the other hand, the buffer layers allow electrode tunneling at higher voltages used for forming and switching signals.

    Abstract translation: 提供了电阻式开关存储单元和形成这种单元的方法。 存储单元包括设置在两个缓冲层之间的电阻式开关层。 用于每个缓冲层的材料的电子势垒高度小于用于电阻式开关层的材料的电子势垒高度。 此外，每个缓冲层的厚度可以小于电阻式开关层的厚度。 缓冲层减少电阻式开关层和电极之间的扩散。 此外，当读取信号被施加到存储器单元时，缓冲层改善数据保持并防止无意的电阻性切换。 读取信号使用低电压，并且在该操作期间大部分电子隧道被缓冲层阻挡。 另一方面，缓冲层允许用于形成和切换信号的较高电压下的电极隧穿。

    SWITCHING COMPONENTS AND MEMORY UNITS
    4.
    发明申请
    SWITCHING COMPONENTS AND MEMORY UNITS 审中-公开
    切换组件和存储单元

    公开(公告)号：WO2015126485A1

    公开(公告)日：2015-08-27

    申请号：PCT/US2014/066177

    申请日：2014-11-18

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： RAMASWAMY, D.V. Nirmal

    IPC: G11C11/14 ,  G11C11/16

    CPC classification number: H01L27/2409 ,  G11C11/16 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148 ,  H01L45/149

    Abstract: Some embodiments include a switching component which includes a selector region between a pair of electrodes. The selector region contains silicon doped with one or more of nitrogen, oxygen, germanium and carbon. Some embodiments include a memory unit which includes a memory cell and a select device electrically coupled to the memory cell. The select device has a selector region between a pair of electrodes. The selector region contains semiconductor doped with one or more of nitrogen, oxygen, germanium and carbon. The select device has current versus voltage characteristics which include snap-back voltage behavior.

    Abstract translation: 一些实施例包括开关组件，其包括一对电极之间的选择器区域。 选择器区域包含掺杂有氮，氧，锗和碳中的一种或多种的硅。 一些实施例包括存储器单元，其包括电存储器单元电存储单元和选择器件。 选择装置在一对电极之间具有选择器区域。 选择器区域包含掺杂有氮，氧，锗和碳中的一种或多种的半导体。 选择器件具有电流对电压特性，其包括回跳电压特性。

    NANOSCALE SWITCHING DEVICE
    8.
    发明申请
    NANOSCALE SWITCHING DEVICE 审中-公开
    纳米开关器件

    公开(公告)号：WO2012036685A1

    公开(公告)日：2012-03-22

    申请号：PCT/US2010/049091

    申请日：2010-09-16

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. ,  RIBEIRO, Gilberto ,  NICKEL, Janice, H. ,  YANG, Jianhua

    Inventor： RIBEIRO, Gilberto ,  NICKEL, Janice, H. ,  YANG, Jianhua

    IPC: H01L27/115 ,  H01L21/8247

    CPC classification number: H01L45/1233 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/148 ,  H01L45/1641

    Abstract: A nanoscale switching device (400) comprises a first electrode (102) of a nanoscale width; a second electrode (108) of a nanoscale width; an active region (106) disposed between the first and second electrodes, the active region containing a switching material; an area (402) within the active region 5 that constrains current flow between the first electrode and the second electrode to a central portion of the active region; and an interlayer dielectric layer (110) formed of a dielectric material and disposed between the first and second electrodes outside the active region. A nanoscale crossbar array (900) and method of forming the nanoscale switching device are also disclosed.

    Abstract translation: 纳米级开关器件（400）包括纳米级宽度的第一电极（102） 具有纳米级宽度的第二电极（108）; 设置在所述第一和第二电极之间的有源区域（106），所述有源区域包含开关材料; 有源区域5内的区域（402），其将第一电极和第二电极之间的电流约束到有源区域的中心部分; 以及由电介质材料形成并且设置在有源区域外部的第一和第二电极之间的层间电介质层（110）。 还公开了一种纳米级交叉串阵列（900）和形成纳米级开关器件的方法。

    CHEMICAL MECHANICAL POLISHING STOP LAYER FOR FULLY AMORPHOUS PHASE CHANGE MEMORY PORE CELL
    10.
    发明申请
    CHEMICAL MECHANICAL POLISHING STOP LAYER FOR FULLY AMORPHOUS PHASE CHANGE MEMORY PORE CELL 审中-公开
    化学机械抛光停止层，用于完全不相变的记忆孔细胞

    公开(公告)号：WO2011025620A1

    公开(公告)日：2011-03-03

    申请号：PCT/US2010/043631

    申请日：2010-07-29

    Applicant: INTERNATIONAL BUSINESS MACHINES CORP. ,  BREITWISCH, Matthew J. ,  LAM, Chung H.

    Inventor： BREITWISCH, Matthew J. ,  LAM, Chung H.

    IPC: H01L21/02 ,  H01L21/321

    CPC classification number: H01L21/31144 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  H01L45/1691

    Abstract: A method for fabricating a phase change memory pore cell that includes forming a bottom electrode, forming a first dielectric layer on the bottom electrode, forming a sacrificial layer on the first dielectric layer, forming an isolation layer on the sacrificial layer, and forming a second dielectric layer on the isolation layer. The method further includes forming a via overlying the bottom electrode, the via extending to the sacrificial layer, etching through the sacrificial layer to the first dielectric layer to form a pore defined extending through the sacrificial layer and the first dielectric layer, depositing phase change material on the sacrificial layer and into the pore and removing the phase change material formed outside the pore, removing the sacrificial layer to expose the pore, the pore being vertically aligned, and forming a top electrode over the pore.

    Abstract translation: 一种相变存储孔单元的制造方法，包括形成底电极，在所述底电极上形成第一电介质层，在所述第一电介质层上形成牺牲层，在所述牺牲层上形成隔离层，形成第二电介质层 隔离层上的介电层。 该方法还包括形成覆盖底部电极的通孔，延伸到牺牲层的通孔，通过牺牲层蚀刻到第一介电层，以形成限定的孔，延伸穿过牺牲层和第一介电层，沉积相变材料 在牺牲层上并进入孔中，除去形成在孔外面的相变材料，去除牺牲层以暴露孔，孔垂直排列，并在孔上形成顶电极。

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