公开(公告)号：WO2022082718A1

公开(公告)日：2022-04-28

申请号：PCT/CN2020/123204

申请日：2020-10-23

Applicant: YANGTZE ADVANCED MEMORY INDUSTRIAL INNOVATION CENTER CO., LTD

Inventor： LIU, Jun

IPC: H01L27/1159 ,  H01L27/11597 ,  G11C11/22

Abstract: A three-dimensional memory including a substrate (310), a stack of alternating stack buffer layers (320) and stack conductor layers (330) formed on the substrate (310), and a channel formed in the stack and extending in a depth direction from a top surface of the stack to a top surface of the substrate (310). The channel may include a channel insulator layer (338) formed on a surface of the stack in the channel and a channel semiconductor layer (340) formed on a surface of the channel insulator layer (338). The stack conductor layer (330) may include a first metal section, a second metal section, and a ferroelectric material (334) positioned between the first metal section and the second metal section.

公开(公告)号：WO2022069986A1

公开(公告)日：2022-04-07

申请号：PCT/IB2021/058437

申请日：2021-09-16

Applicant: 株式会社半導体エネルギー研究所

Inventor： 山崎舜平 ,  池田隆之 ,  大貫達也 ,  國武寛司 ,  神保安弘

IPC: H01L27/11597 ,  H01L21/336 ,  H01L29/788 ,  H01L29/792 ,  H01L29/786

Abstract: 記憶容量の大きい記憶装置を提供する。信頼性の高い記憶装置を提供する。 半導体装置は、第１の方向に延在する第１の導電層と、第１の方向と交差する第２の方向に延在する構造体と、第１の絶縁層及び第２の絶縁層と、を有する。構造体は、機能層と、半導体層と、第３の絶縁層と、第２の導電層と、を有する。第１の導電層と、構造体との交差部において、第２の導電層を中心に、第３の絶縁層、半導体層、及び機能層が、この順で同心円状に配置される。また、第１の絶縁層と、第２の絶縁層は、第２の方向に積層される。機能層と、第１の導電層とは、第１の絶縁層と第２の絶縁層との間に配置される。第２の導電層、第３の絶縁層、及び半導体層は、第１の絶縁層に設けられた第１の開口の内側に位置する部分と、第２の絶縁層に設けられた第２の開口の内側に位置する部分と、を有する。

公开(公告)号：WO2022000344A1

公开(公告)日：2022-01-06

申请号：PCT/CN2020/099586

申请日：2020-06-30

Applicant: 华为技术有限公司

Inventor： 景蔚亮 ,  王正波 ,  崔靖杰

IPC: H01L27/11597

Abstract: 本申请的实施例提供一种存储器及其制造方法，涉及存储领域，该方案提供的存储器可以直接通过环绕栅极纳米线制造技术制造。该存储器，包括：堆叠层，堆叠层包括交叠设置的第一导电层和第二导电层，以及设置在相邻的第一导电层和第二导电层之间的隔离层；堆叠层包括贯穿堆叠层的垂直通道，垂直通道的内侧侧壁上形成有半导体薄膜；第一导电层包括导电材料，第一导电层的导电材料与半导体薄膜之间形成有电荷捕获膜层，半导体薄膜在与电荷捕获膜层相对的位置上形成有贯穿半导体薄膜的沟道，第二导电层包含导电材料，半导体薄膜与第二导电层的导电材料接触的位置形成有电极结构，电极结构包括源极或漏极。

公开(公告)号：WO2021246664A1

公开(公告)日：2021-12-09

申请号：PCT/KR2021/005621

申请日：2021-05-04

Applicant: 한양대학교 산학협력단

Inventor： 송윤흡 ,  김봉석 ,  심재민 ,  최선준

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/285 ,  H01L21/768 ,  H01L27/1159 ,  H01L27/11592 ,  H01L27/11597 ,  H01L27/11568

Abstract: 누설 전류를 개선하는 3차원 플래시 메모리 및 기판이 개시된다. 3차원 플래시 메모리는 기판 상 일 방향으로 연장 형성되는 스트링-상기 스트링은 상기 일 방향으로 연장 형성되는 채널층 및 상기 채널층을 감싸도록 상기 일 방향으로 연장 형성되는 전하 저장층을 포함함-; 상기 스트링의 상단 또는 하단에 수직으로 연결되는 적어도 하나의 선택 라인(Selection Line); 및 상기 적어도 하나의 선택 라인의 상부 또는 하부에 위치한 채 상기 스트링에 수직으로 연결되는 복수의 워드 라인들을 포함하고, 상기 채널층은, 산화물 반도체 물질로 형성되는 것을 특징으로 한다.

公开(公告)号：WO2021194996A1

公开(公告)日：2021-09-30

申请号：PCT/US2021/023535

申请日：2021-03-22

Applicant: HSU, Fu-Chang

Inventor： HSU, Fu-Chang

IPC: H01L27/11551 ,  H01L27/11553 ,  H01L27/11563 ,  H01L27/11578 ,  H01L27/1158 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/2273 ,  G11C11/2275 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/26 ,  G11C17/18 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/11206 ,  H01L27/11582 ,  H01L27/11597 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/249

Abstract: A three dimensional double-density memory array is disclosed. In an embodiment, a three-dimensional (3D) double density array comprises a string of memory devices that are configured so that a first portion of the memory devices form a first channel and a second portion of the memory devices form a second channel. The array also comprises a plurality of word lines coupled to the string of memory devices. Each word line is coupled to a memory device that forms the first channel and a memory device that forms the second channel. The array also comprises at least one drain select gate that couples the first and second channels to a bit line.

公开(公告)号：WO2021173176A1

公开(公告)日：2021-09-02

申请号：PCT/US2020/039003

申请日：2020-06-22

Applicant: SANDISK TECHNOLOGIES LLC.

Inventor： RABKIN, Peter ,  HIGASHITANI, Masaaki ,  KALITSOV, Alan

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L29/78 ,  H01L29/51

Abstract: A ferroelectric memory device includes a two-dimensional electron gas channel, a gate electrode, and a ferroelectric element located between the gate electrode and the two-dimensional electron gas channel.

公开(公告)号：WO2021142747A1

公开(公告)日：2021-07-22

申请号：PCT/CN2020/072624

申请日：2020-01-17

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： LU, Feng ,  GAO, Jing ,  ZHOU, Wenbin

IPC: H01L27/11597 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method for forming a three-dimensional (3D) memory device is disclosed. In some embodiments, the method includes forming an alternating dielectric stack on a substrate, and forming a plurality of channel holes penetrating the alternating dielectric stack vertically to expose at least a portion of the substrate. A first mask can be formed to cover the channel holes in a first area and expose the channel holes in a second area. The method also includes forming a recess in the alternating dielectric stack in the second area, followed by forming a second mask in the recess. The second mask covers the channel holes in the second area and exposes the channel holes in the first area. The memory film at bottom of each channel hole in the first area can therefore be removed, while the memory film in the second area can be protected by the second mask.

公开(公告)号：WO2021141612A1

公开(公告)日：2021-07-15

申请号：PCT/US2020/034798

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： ZHANG, Yanli ,  ALSMEIER, Johann ,  ZHOU, Fei

IPC: G11C11/40 ,  H01L21/8238 ,  H01L29/78 ,  G11C11/223 ,  H01L27/11587 ,  H01L27/11597 ,  H01L29/6684 ,  H01L29/78391

Abstract: A semiconductor structure includes layer stack structures laterally extending along a first horizontal direction and spaced apart from each other along a second horizontal direction by line trenches. Each of the layer stack structures includes at least one instance of a unit layer sequence that includes, from bottom to top or top to bottom, a doped semiconductor source strip, a channel-level insulating strip, and a doped semiconductor drain strip. Line trench fill structures are located within a respective one of the line trenches. Each of the line trench fill structures includes a laterally-alternating sequence of memory pillar structures and dielectric pillar structures. Each of the memory pillar structures includes a gate electrode, at least one pair of ferroelectric dielectric layers, and at least one pair of vertical semiconductor channels located at each level of the channel-level insulating strips.

公开(公告)号：WO2021133427A1

公开(公告)日：2021-07-01

申请号：PCT/US2020/025933

申请日：2020-03-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： RAJASHEKHAR, Adarsh ,  ZHOU, Fei ,  MAKALA, Raghuveer S. ,  ZHANG, Yanli ,  SHARANGPANI, Rahul

IPC: H01L27/1158 ,  H01L27/11568 ,  H01L27/11521 ,  H01L27/11553 ,  H01L29/792 ,  H01L29/788 ,  H01L29/66 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597 ,  H01L29/41741

Abstract: A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, memory openings vertically extending through the alternating stack, vertical word lines located in each one of the memory openings and vertically extending through each of the source layers and the drain layers of the alternating stack, vertical stacks of discrete semiconductor channels located in each one of the memory openings and contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers, and vertical stacks of discrete memory material portions located in each one of the memory openings and laterally surrounding a respective one of the vertical word lines. Each memory material portion is laterally spaced from a respective one of the semiconductor channels by a respective gate dielectric layer.

公开(公告)号：WO2021107973A1

公开(公告)日：2021-06-03

申请号：PCT/US2020/024813

申请日：2020-03-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： ZHANG, Yanli ,  ALSMEIER, Johann

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  G11C11/22

Abstract: A ferroelectric field effect transistor (FeFET) includes a semiconductor channel, a source region contacting one end of the semiconductor channel, a drain region contacting a second end of the semiconductor channel, a gate electrode, a ferroelectric gate dielectric layer located between the semiconductor channel and the gate electrode, and a bidirectional selector material layer located between the gate electrode and the ferroelectric gate dielectric layer.