公开(公告)号：WO2014099322A1

公开(公告)日：2014-06-26

申请号：PCT/US2013/072421

申请日：2013-11-27

Applicant: SUNPOWER CORPORATION ,  WU, Junbo ,  JOHNSON, Michael C. ,  CUDZINOVIC, Michael ,  BEHNKE, Joseph ,  ZHU, Xi ,  SMITH, David D. ,  SEWELL, Richard Hamilton ,  TU, Xiuwen ,  RIM, Seung Bum

Inventor： WU, Junbo ,  JOHNSON, Michael C. ,  CUDZINOVIC, Michael ,  ZHU, Xi ,  SMITH, David D. ,  SEWELL, Richard Hamilton ,  TU, Xiuwen ,  RIM, Seung Bum

IPC: H01L31/04 ,  H01L31/18

CPC classification number: H01L31/022425 ,  H01L31/02167 ,  H01L31/022441 ,  H01L31/0682 ,  H01L31/1864 ,  Y02E10/50 ,  Y02E10/547

Abstract: Enhanced adhesion of seed layers for solar cell conductive contacts and methods of forming solar cell conductive contacts are described. For example, a method of fabricating a solar cell includes forming an adhesion layer above an emitter region of a substrate. A metal seed paste layer is formed on the adhesion layer. The metal seed paste layer and the adhesion layer are annealed to form a conductive layer in contact with the emitter region of the substrate. A conductive contact for the solar cell is formed from the conductive layer.

Abstract translation: 描述了用于太阳能电池导电触点的种子层的增强的附着和形成太阳能电池导电触点的方法。 例如，制造太阳能电池的方法包括在基板的发射极区域的上方形成粘附层。 在粘合层上形成金属种子糊层。 将金属种子糊层和粘附层退火以形成与衬底的发射极区域接触的导电层。 用于太阳能电池的导电接触由导电层形成。

公开(公告)号：WO2014098999A1

公开(公告)日：2014-06-26

申请号：PCT/US2013/047388

申请日：2013-06-24

Applicant: INTEL CORPORATION

Inventor： DOYLE, Brian S. ,  KOTLYAR, Roza ,  SHAH, Uday ,  KUO, Charles C.

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7827 ,  B82Y10/00 ,  H01L21/0237 ,  H01L21/02636 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  Y10S977/762

Abstract: Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.

Abstract translation: 垂直取向的纳米线晶体管包括具有在晶体管的长度上变化的组成的半导体层或栅电极。 在实施例中，晶体管沟道区域沿着沟道的长度成分地分级或分层以诱导应变，和/或包括高迁移率注入层。 在实施例中，沉积包括多个栅电极材料的栅极电极堆叠以沿着栅极长度调制栅电极功函数。

公开(公告)号：WO2014051814A1

公开(公告)日：2014-04-03

申请号：PCT/US2013/048655

申请日：2013-06-28

Applicant: INTEL CORPORATION ,  SISTLA, Krishnakanth ,  ROWLAND, Martin Mark ,  ROTEM, Efraim ,  GRIFFITH, Brian J. ,  VARMA, Ankush ,  SURYANARAYANAN, Anupama

Inventor： SISTLA, Krishnakanth ,  ROWLAND, Martin Mark ,  ROTEM, Efraim ,  GRIFFITH, Brian J. ,  VARMA, Ankush ,  SURYANARAYANAN, Anupama

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/329 ,  Y02D10/152 ,  Y02D10/24

Abstract: A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.

Abstract translation: 描述了一种处理器，其包括从处理器的输入到处理器内的逻辑电路的快速信号路径。 输入是接收一个快速的减速信号。 逻辑电路是为了降低处理器响应于快速减速信号而执行指令的速率。 快速信号路径是在处理器内施加实际上最小的快速降低信号的传播延迟。

公开(公告)号：WO2014051780A1

公开(公告)日：2014-04-03

申请号：PCT/US2013/047629

申请日：2013-06-25

Applicant: INTEL CORPORATION ,  ANANTHAKRISHNAN, Avinash N. ,  SEBOT, Julien Fefe ,  SCHWARTZ, Jay D. ,  GUNTHER, Stephen H. ,  SAMSON, Eric C.

Inventor： ANANTHAKRISHNAN, Avinash N. ,  SEBOT, Julien Fefe ,  SCHWARTZ, Jay D. ,  GUNTHER, Stephen H. ,  SAMSON, Eric C.

IPC: G06F1/26 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F1/3293 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/171

Abstract: A processor is described that includes a plurality of execution cores. The processor also includes power management circuitry to dynamically determine a number of the execution cores that, when active, will cause the processor to operate in a substantially linear power consumption vs. frequency region of operation such that performance gain as a function of power consumption increase with the number of cores is higher as compared to any other number of active execution cores within an established power envelope.

Abstract translation: 描述了包括多个执行核心的处理器。 处理器还包括电源管理电路，用于动态地确定许多执行核心，当激活时，这些核心将使得处理器以基本上线性的功率消耗与频率操作区域相互作用，使得作为功率消耗的功能的性能增益 与所建立的功率范围内的任何其他数量的主动执行核心相比，核心数量更高。

公开(公告)号：WO2014051773A1

公开(公告)日：2014-04-03

申请号：PCT/US2013/047430

申请日：2013-06-24

Applicant: INTEL CORPORATION

Inventor： PILLARISETTY, Ravi ,  GOEL, Niti ,  THEN, Han Wui ,  LE, Van H. ,  RACHMADY, Willy ,  RADOSAVLJEVIC, Marko ,  DEWEY, Gilbert ,  CHU-KUNG, Benjamin

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/775 ,  B82Y10/00 ,  H01L21/28255 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/785 ,  H01L29/78696

Abstract: Semiconductor devices having germanium active layers with underlying parasitic leakage barrier layers are described. For example, a semiconductor device includes a first buffer layer disposed above a substrate. A parasitic leakage barrier is disposed above the first buffer layer. A second buffer layer is disposed above the parasitic leakage barrier. A germanium active layer is disposed above the second buffer layer. A gate electrode stack is disposed above the germanium active layer. Source and drain regions are disposed above the parasitic leakage barrier, on either side of the gate electrode stack.

Abstract translation: 描述具有底层寄生泄漏阻挡层的具有锗活性层的半导体器件。 例如，半导体器件包括设置在衬底上方的第一缓冲层。 寄生泄漏屏障设置在第一缓冲层之上。 第二缓冲层设置在寄生泄漏屏障的上方。 锗活性层设置在第二缓冲层上方。 栅电极堆叠设置在锗活性层上方。 源极和漏极区域设置在栅极电极堆叠的任一侧上的寄生泄漏屏障之上。

公开(公告)号：WO2014051770A1

公开(公告)日：2014-04-03

申请号：PCT/US2013/047396

申请日：2013-06-24

Applicant: INTEL CORPORATION

Inventor： SARANGSHAR, Nitin V.

IPC: G06F21/70 ,  G06F9/24 ,  G06F9/445

CPC classification number: G06F9/4401

Abstract: Embodiments of the invention describe apparatuses, systems and method for particularly to providing alternative boot paths for computing devices. In embodiments of the invention, a non-volatile controller subsystem is powered up by default in order to allow memory operations to one or more non-volatile devices prior to PCIe/USB enumeration. Logic such as a system SPI controller receives a request to access an SPI flash device for executing a firmware image instruction; however, embodiments of the invention either do not include or do not utilize an SPI flash device. Instead of notifying an SPI flash device, the host SPI controller redirects this request to the non-volatile controller subsystem. The non-volatile controller accesses one or more non-volatile device(s) for executing the firmware image instruction. Furthermore, embodiments of the invention may also support the protection of storage operations initiated from the host controller to the non-volatile device from hardware attacks.

Abstract translation: 本发明的实施例描述了特别用于为计算设备提供替代的引导路径的设备，系统和方法。 在本发明的实施例中，非易失性控制器子系统默认上电，以便在PCIe / USB枚举之前允许对一个或多个非易失性设备的存储器操作。 诸如系统SPI控制器的逻辑接收访问SPI闪存器件以执行固件映像指令的请求; 然而，本发明的实施例不包括或不使用SPI闪存设备。 主机SPI控制器不是通知SPI闪存设备，而是将该请求重定向到非易失性控制器子系统。 非易失性控制器访问用于执行固件图像指令的一个或多个非易失性设备。 此外，本发明的实施例还可以支持从主机控制器向非易失性设备发起的从硬件攻击发起的存储操作的保护。

公开(公告)号：WO2014051769A1

公开(公告)日：2014-04-03

申请号：PCT/US2013/047385

申请日：2013-06-24

Applicant: INTEL CORPORATION

Inventor： GOEL, Niti ,  PILLARISETTY, Ravi ,  MUKHERJEE, Niloy ,  CHAU, Robert S. ,  RACHMADY, Willy ,  METZ, Matthew V. ,  LE, Van H. ,  KAVALIEROS, Jack T. ,  RADOSAVLJEVIC, Marko ,  CHU-KUNG, Benjamin ,  DEWEY, Gilbert ,  SUNG, Seung Hoon

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/0245 ,  H01L21/02538 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

Abstract translation: 一种装置，包括在具有与第一格子结构不同的第二格子结构的缓冲材料中具有匹配的晶格结构的阱材料的阱上具有第一晶格结构的沟道材料的装置。 一种包括在缓冲材料中形成沟槽的方法; 在沟槽中形成n型阱材料，n型阱材料具有与缓冲材料的晶格结构不同的晶格结构; 并形成n型晶体管。 一种包括计算机的系统，包括处理器，所述处理器包括互补的金属氧化物半导体电路，所述辅助金属氧化物半导体电路包括包括沟道材料的n型晶体管，所述沟道材料在布置在具有不同于 第一晶格结构，n型晶体管耦合到p型晶体管。

公开(公告)号：WO2014051761A1

公开(公告)日：2014-04-03

申请号：PCT/US2013/046896

申请日：2013-06-20

Applicant: INTEL CORPORATION

Inventor： THEN, Han Wui ,  DASGUPTA, Sansaptak ,  SCHROM, Gerhard ,  RAO, Valluri R. ,  CHAU, Robert S.

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/0605 ,  H01L27/0805 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66181 ,  H01L29/93 ,  H01L29/94

Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

Abstract translation: 集成了至少一个具有高击穿电压（BV）的III-N MOS电容器的III-N高压MOS电容器和片上系统（SoC）解决方案，以实现高压和/或高功率电路。 可以实现超过4V的击穿电压，避免了RFIC和/或PMIC中的串联耦合电容的任何需要。 在实施例中，包括其中在低于0V的阈值电压下形成二维电子气（2DEG）的GaN层的耗尽型III-N电容器与IV族晶体管架构单片集成，例如平面和非平面硅CMOS晶体管技术 。 在实施例中，蚀刻硅衬底以提供形成GaN层和III-N势垒层的（111）外延生长表面。 在实施例中，沉积高K电介质层，并且电容器端子触点被制成2DEG并且在电介质层上。

公开(公告)号：WO2014051732A1

公开(公告)日：2014-04-03

申请号：PCT/US2013/045427

申请日：2013-06-12

Applicant: INTEL CORPORATION

Inventor： DASGUPTA, Sansaptak ,  THEN, Han Wui ,  RADOSAVLJEVIC, Marko ,  MUKHERJEE, Niloy ,  GOEL, Niti ,  KABEHIE, Sanaz ,  SUNG, Seung Hoon ,  PILLARISETTY, Ravi ,  CHAU, Robert S.

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/7784 ,  H01L21/0254 ,  H01L21/2233 ,  H01L21/2236 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.

Abstract translation: 实施例包括高电子迁移率晶体管（HEMT）。 在实施例中，栅电极与源极和漏极半导体区间隔开不同的距离以提供高击穿电压和低导通状态电阻。 在实施例中，应用自对准技术以在沟槽中和在中间心轴上形成电介质衬垫，以通过单个掩蔽操作独立地限定栅极长度，栅极源长度和栅极 - 漏极长度。 在实施例中，III-N HEMT包括用于阈值电压调谐和/或增强模式操作的氟掺杂半导体势垒层。

公开(公告)号：WO2014042730A1

公开(公告)日：2014-03-20

申请号：PCT/US2013/045511

申请日：2013-06-12

Applicant: SALESFORCE.COM, INC.

Inventor： WANG, Xiaodan ,  DEVADHAR, Vijayanth ,  MURUGESAN, Praveen

IPC: G06F9/50

CPC classification number: G06F9/50 ,  G06F9/5027 ,  G06F2209/508 ,  G06Q30/08 ,  H04L43/08 ,  H04L47/70

Abstract: In accordance with embodiments, there are provided mechanisms and methods for facilitating sliding window resource tracking in message queues for fair management of resources for application servers in an on-demand services environment. In one embodiment and by way of example, a method includes monitoring, in real-time, in-flight jobs in message queues for incoming jobs from organizations in a distributed environment having application servers in communication over a network, applying local sliding windows to the message queues to estimate wait time associated with each incoming job in a message queue. A local sliding window may include segment of time being monitored in each message queue for estimating the wait time. The method may further include allocating, in real-time, based on the estimated wait time, thread resources to one or more of the incoming jobs associated with the one or more of the organizations.

Abstract translation: 根据实施例，提供了用于促进消息队列中的滑动窗口资源跟踪以用于按需服务环境中的应用服务器的资源的公平管理的机制和方法。 在一个实施例中，作为示例，一种方法包括实时地监视来自具有通过网络通信的应用服务器的分布式环境中的组织的来自作业的消息队列中的飞行中作业，将本地滑动窗口应用于 消息队列来估计与消息队列中的每个传入作业相关联的等待时间。 本地滑动窗口可以包括在每个消息队列中被监视的时间段，用于估计等待时间。 该方法可以进一步包括实时地基于估计的等待时间将线程资源分配给与一个或多个组织相关联的一个或多个进入作业。