公开(公告)号：WO9008362A3

公开(公告)日：1990-09-07

申请号：PCT/US9000266

申请日：1990-01-12

Applicant: VLSI TECHNOLOGY INC

Inventor： ASATO CREIGHTON SATOSHI ,  DHOLAKIA SURESH KISHORBHAI ,  DITZEN CHRISTOPH

IPC: G06F7/53 ,  G06F7/00 ,  G06F7/506 ,  G06F7/527 ,  G06F9/38 ,  G06F17/50 ,  G06F15/60

CPC classification number: G06F17/5045 ,  G06F7/00 ,  G06F9/3875

Abstract: According to a technique for determining delays through multi-stage datapath elements, estimates of the delays through each stage of the datapath element are computed in accordance with an equation such as: Ds=DbNb+C; where Ds is the estimated stage delay, Db is a delay associated with communication between bits in the stage, Nb is the number of bits in the datapath element, and C is a constant. The estimated stage delays are used to determine positions of pipelining stages in the datapath element.

公开(公告)号：WO1996021183A1

公开(公告)日：1996-07-11

申请号：PCT/US1996000269

申请日：1996-01-03

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  TAKAHASHI, Richard, J.

IPC: G06F01/02

CPC classification number: G06F1/02 ,  G06F2101/14

Abstract: A randomizer system (10) generates an undeterministic data block using standard cell library units and includes a random number generator (20). The generator includes at least two metastable blocks that each include a plurality of D-type flip-flops. Each flip-flop is coupled to a dedicated free-running oscillator and common jitter clock. The flip-flops are thus forcibly operated in a metastable state by intentionally violating the flip-flop set-up or hold time margins of incoming data related to the jitter clock. The flip-flop outputs are exclusively "OR"d and then passed through first and second shift registers of uneven and preferably even and odd bit lengths. The input from each shift register is then EX-OR'd and clocked out with a system clock to provide first and second channels of undeterministic data.

Abstract translation: 随机化系统（10）使用标准单元库单元生成不确定数据块，并且包括随机数发生器（20）。 发生器包括至少两个亚稳态块，每个块包括多个D型触发器。 每个触发器耦合到专用的自由运行振荡器和常见的抖动时钟。 触发器因此有意地违反触发器设置或保持与抖动时钟相关的输入数据的时间余量而强制地在亚稳状态下操作。 触发器输出仅为“或”d，然后通过不均匀，优选偶数和奇数位长度的第一和第二移位寄存器。 然后，每个移位寄存器的输入被异或运算并用系统时钟输出，以提供第一和第二通道的不确定数据。

公开(公告)号：WO1996019828A1

公开(公告)日：1996-06-27

申请号：PCT/US1995016587

申请日：1995-12-19

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  GROOVER, Richard, L. ,  PRESTON, Matthew, Wayne

IPC: H01L23/495

CPC classification number: H01L23/24 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Lead systems of the subject invention include "coplanar leads" (12C) and "aplanar leads" (12A), which differ in structure at the inner bond finger. Coplanar leads (12C) are generally planar along the lead body (12) and the inner bond finger. Aplanar leads (12A) are bent or deformed at the inner bond finger, such that the inner bond finger terminus is not in the plane of the lead body (12) but instead is above or below the plane of the lead body. Deforming select inner bond fingers out of the general plane of the lead system provides a spatial separation for the bonding wires (22) which are attached to the inner bond fingers. This spatial separation acts to minimize wire crossing and shorting during fill processes and results in improved semiconductor package yield.

Abstract translation: 本发明的引线系统包括在内部键合指状结构上不同的“共面引线”（12C）和“平面引线”（12A）。 共面引线（12C）沿引线本体（12）和内键指通常是平面的。 平面引线（12A）在内键指处弯曲或变形，使得内键指末端不在引线体（12）的平面内，而是位于引线体的平面之上或之下。 使引导系统的一般平面内的选择的内部粘合指状物的变形为连接到内部粘结指状物的接合线（22）提供空间分离。 这种空间分离用于使填充过程中的电线交叉和短路最小化，并导致提高的半导体封装产量。

公开(公告)号：WO1996013904A1

公开(公告)日：1996-05-09

申请号：PCT/EP1995004248

申请日：1995-10-26

Applicant: VLSI TECHNOLOGY INC. ,  VLSI TECHNOLOGY S.A.R.L.

Inventor： VLSI TECHNOLOGY INC. ,  VLSI TECHNOLOGY S.A.R.L. ,  GINETTI, Bernard

IPC: H03M01/74

CPC classification number: H03M1/685 ,  H03M1/747

Abstract: A digital-analog converter incorporates an array of current source cells connected at the output to a load as a function of an input code subdivided into respectively H and V, most significant bit (MSB) and least significant bit (LSB), converted into thermometric codes, respectively HT and VT, whose logic inverses are respectively horizontally and vertically routed to said array. Each position cell (h, v) comprises a first and a second P type metal oxide semiconductor field effect transistor in series, in parallel with at least one third P type metal oxide semiconductor field effect transistor.

Abstract translation: 数字模拟转换器将在输出端连接到负载的电流源单元阵列作为分为H和V，最高有效位（MSB）和最低有效位（LSB））的输入代码的函数组合，转换成温度计 代码分别为HT和VT，其逻辑反转分别水平和垂直地路由到所述阵列。 每个位置单元（h，v）包括与至少一个第三P型金属氧化物半导体场效应晶体管并联的第一和第二P型金属氧化物半导体场效应晶体管。

公开(公告)号：WO1996010784A1

公开(公告)日：1996-04-11

申请号：PCT/US1995011969

申请日：1995-09-19

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  DOCKSER, Kenneth, A.

IPC: G06F09/302

CPC classification number: G06F7/57 ,  G06F7/02 ,  G06F7/49905 ,  G06F7/505 ,  G06F9/3001

Abstract: An arithmetic logic unit (ALU) provides for zero-result prediction so as to eliminate the latency between sucessive operations (e.g., multiplication and division) when a zero detection is a condition for performance of the second operation. Instead of performing zero detection on the result, zero prediction is performed on the initial or intermediate operands, (e.g., partial products that are summed to generate a product). To this end, zero-prediction logic (ZP) determines whether or not both of the following conditions are met: 1) either the least significant bits of the addends are the same and the carry-in is zero or the least significant bits of the addends are different and the carry-in is one; 2) for each pair of adjacent bit positions, the four included bits are consistent with addend complementarity. If both conditions are met, a zero result is predicted; otherwise, a non-zero result is predicted.

Abstract translation: 算术逻辑单元（ALU）提供零结果预测，以便当零检测是用于执行第二操作的条件时，消除成功操作（例如，乘法和除法）之间的等待时间。 不是对结果执行零检测，而是对初始或中间操作数执行零预测（例如，求和以产生产品的部分乘积）。 为此，零预测逻辑（ZP）确定是否满足以下两个条件：1）加数的最低有效位是相同的，并且进位是零或最低有效位 加数是不同的，进位是一个; 2）对于每对相邻位位置，四个包含的位与加数互补一致。 如果满足这两个条件，则预测为零结果; 否则，预测非零结果。

公开(公告)号：WO1995027306A1

公开(公告)日：1995-10-12

申请号：PCT/US1995003704

申请日：1995-03-27

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  HAN, Yu-Pin ,  NAGALINGAM, Samuel, J., S.

IPC: H01L21/336

CPC classification number: H01L29/66575 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  Y10S148/018

Abstract: The punchthrough capacity of a p-type semiconductor device is significantly improved by nonuniformly doping the p-channel with n-type implants such as phosphorus. The n-type dopants are implanted at large angles to form pocket implants within the channel region. The dose of the implants, angle of the implants and the thermal cycle annealing of the implants will be optimized for maximum punchthrough capability without substantially detracting from the performance of the semiconductor device.

Abstract translation: p型半导体器件的穿透能力通过使用n型植入物例如磷不均匀掺杂p沟道而显着提高。 n型掺杂剂以大角度植入，以在沟道区内形成袋状植入物。 植入物的剂量，植入物的角度和植入物的热循环退火将针对最大穿透能力而优化，而不会显着降低半导体器件的性能。

公开(公告)号：WO1995026533A1

公开(公告)日：1995-10-05

申请号：PCT/US1994014968

申请日：1994-12-27

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  MISHELOFF, Michael, Norman

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: A method determines approximate propagation delay through logic cells (30, 31) within a library. Each logic cell (30) within the library is characterized at baseline conditions to obtain parameters for each logic cell (30) which define propagation delay through each logic cell (30) at the baseline conditions. A subset of the logic cells (30) are characterized at conditions varying from the baseline conditions to obtain scaling parameters. The scaling parameters modify values of the parameters for all logic cells (30) within the library in order to approximate changes in propagation delay through each logic cell (30) resulting from changes in the baseline conditions. In the preferred embodiment, the conditions varying from the baseline conditions includes a change in at least one of operating temperature, power supply voltage and process conditions.

Abstract translation: 一种方法通过库内的逻辑单元（30,31）来确定近似的传播延迟。 库内的每个逻辑单元（30）在基线条件下表征，以获得每个逻辑单元（30）的参数，其在基线条件下定义通过每个逻辑单元（30）的传播延迟。 逻辑单元（30）的子集在从基线条件变化的条件下表征，以获得缩放参数。 缩放参数修改库内所有逻辑单元（30）的参数的值，以便近似由基准条件变化导致的每个逻辑单元（30）的传播延迟的变化。 在优选实施例中，从基线条件变化的条件包括工作温度，电源电压和工艺条件中的至少一个的变化。

公开(公告)号：WO1995024032A1

公开(公告)日：1995-09-08

申请号：PCT/US1995000613

申请日：1995-01-17

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  CAIN, Bradley, W. ,  JAYAVANT, Rajeev ,  RHODEN, William, Desi

IPC: G09G01/16

CPC classification number: G09G5/393

Abstract: An image is written to a data frame buffer (18) for display by a monitor (19). The image includes a repeated pattern. The present invention uses a repeated pattern cache (22) which is not large enough to simultaneously contain an entire repeated pattern. When writing a pixel of the image, a horizontal pattern offset and a vertical pattern offset for a destination location of the pixel are determined. If a scan line for the repeated pattern which corresponds to the vertical pattern offset does not reside in the repeated pattern cache (22), the scan line for the repeated pattern which corresponds to the vertical pattern offset is fetched into the repeated pattern cache (22). When the scan line for the repeated pattern which corresponds to the vertical pattern offset resides in the repeated pattern cache (22), the pixel is accessed at a location in the repeated pattern cache (22) at a location which corresponds to the horizontal pattern offset. The accessed pixel is written to the buffer (18).

Abstract translation: 将图像写入数据帧缓冲器（18），以由监视器（19）显示。 图像包括重复的图案。 本发明使用不足以同时包含整个重复模式的重复模式高速缓存（22）。 当写入图像的像素时，确定用于像素的目的地位置的水平图案偏移和垂直图案偏移。 如果对应于垂直图案偏移的重复图案的扫描线不驻留在重复图案高速缓存（22）中，则对应于垂直图案偏移的重复图案的扫描线被提取到重复图案高速缓存（22 ）。 当对应于垂直图案偏移的重复图案的扫描线位于重复图案高速缓存（22）中时，在重复图案高速缓存（22）的位置处，在与水平图案偏移对应的位置处访问像素 。 所访问的像素被写入缓冲器（18）。

公开(公告)号：WO1995023976A1

公开(公告)日：1995-09-08

申请号：PCT/US1995000614

申请日：1995-01-18

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  EBZERY, Thomas, J.

IPC: G01R31/28

CPC classification number: H03K3/356156 ,  H03K3/0375

Abstract: A flip-flop has both a system output (55, 95, 145) and a scan output (56, 96, 146). A system output signal for the flip-flop is placed on the system output (55, 95, 145). When the flip-flop is in a normal operating mode, a scan output signal on the scan output (56, 96, 146) is held at a static logic level. When the flip-flop is in a scan mode, the scan output signal on the scan output (56, 96, 146) transitions between logic 1 and logic 0 synchronous with transitions of the system output signal on the system output (55, 95, 145).

Abstract translation: 触发器具有系统输出（55,95,145）和扫描输出（56,96,146）。 触发器的系统输出信号被放置在系统输出（55,95，145）上。 当触发器处于正常操作模式时，扫描输出（56,96,146）上的扫描输出信号保持在静态逻辑电平。 当触发器处于扫描模式时，扫描输出（56,96,146）上的扫描输出信号在逻辑1和逻辑0之间转换，与系统输出上的系统输出信号的转换同步（55,95， 145）。

公开(公告)号：WO1995015527A1

公开(公告)日：1995-06-08

申请号：PCT/US1994013550

申请日：1994-11-23

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  LEHMAN, Judson ,  WU, Shih-Ho

IPC: G06F13/16

CPC classification number: G06F13/1684 ,  G06F12/023

Abstract: The present invention provides a low-cost computer system which includes a single shared memory that can be independently accessible as graphics memory or main store system memory without performance degradation. Because the "appetite" for main system memory (unlike that of a display memory) is difficult to satisfy, the memory granularity problem can be addressed by programmably reallocating an unused portion of a display memory for system memory use. Reallocation of the unused display memory alleviates any need to oversize the display memory, yet realizes the cost effectiveness of using readily available memory sizes. Further, reallocation of the graphics memory avoids any need to separately consider both the system memory and the display memory in accommodating worst case operational requirements.

Abstract translation: 本发明提供了一种低成本计算机系统，其包括单独的共享存储器，其可以作为图形存储器或主存储系统存储器独立地访问而没有性能下降。 由于主系统存储器（与显示存储器不同）的“胃口”难以满足，所以存储器粒度问题可以通过可编程地重新分配用于系统存储器使用的显示存储器的未使用部分来解决。 未使用的显示存储器的重新分配减轻了对显示存储器进行超大尺寸的任何需求，但是实现了使用容易获得的存储器大小的成本效益。 此外，重新分配图形存储器避免了在适应最坏情况操作要求时单独考虑系统存储器和显示存储器的任何需要。