Abstract:
Integrated device having GDT and MOV functionalities. In some embodiments, an electrical device can include a first layer and a second layer joined with an interface, with each having an outer surface and an inner surface, such that the inner surfaces of the first and second layers define a sealed chamber therebetween. The electrical device can further include an outer electrode implemented on the outer surface of each of the first and second layers, and an inner electrode implemented on the inner surface of each of the first and second layers. The first layer can include a metal oxide material such that the first outer electrode, the first layer, and the first inner electrode provide a metal oxide varistor (MOV) functionality, and the first inner electrode, the second inner electrode, and the sealed chamber provide a gas discharge tube (GDT) functionality.
Abstract:
Through-mold features for shielding applications. In some embodiments, a packaged module can include a packaging substrate having a ground plane, and one or more contact pads implemented on an upper side and electrically connected to the ground plane. The module can further include a radio-frequency circuit assembly implemented on the upper side of the packaging substrate, and an overmold implemented on the upper side of the packaging substrate to cover the one or more contact pads and the radio-frequency circuit assembly. The module can further include a conductive layer configured to cover an upper surface of the overmold and one or more through-mold features, with each being configured to provide an electrical connection between the conductive layer and the ground plane through the corresponding contact pad, to thereby provide shielding between a first location within the module and a second location relative to the module.
Abstract:
Silicon-on-insulator (SOI) devices having contact layer. In some embodiments, a radio-frequency (RF) device can include a field-effect transistor (FET) implemented over a substrate layer, and an insulator layer implemented between the FET and the substrate layer. The RF device can further include a contact layer implemented between the insulator layer and the substrate layer to allow adjustment of RF performance of the FET. In some embodiments, such an RF device can be implemented as an RF switch in various products such as a die, a packaged module, and a wireless device.
Abstract:
Power amplifier having staggered cascode layout for enhanced thermal ruggedness. In some embodiments, a radio-frequency (RF) amplifier such as a power amplifier (PA) can be configured to receive and amplify an RF signal. The PA can include an array of cascoded devices connected electrically parallel between an input node and an output node. Each cascoded device can include a common emitter transistor and a common base transistor arranged in a cascode configuration. The array can be configured such that the common base transistors are positioned in a staggered orientation relative to each other.
Abstract:
According to some implementations, a power amplifier (PA) includes a common emitter configured to receive a radio-frequency (RF) signal. The PA also includes a carrier amplifier coupled to the common emitter to form a carrier cascode configuration, a collector of the carrier amplifier provided with a first supply voltage. The PA further includes a peaking amplifier coupled to the common emitter to form a peaking cascode configuration, a collector of the peaking amplifier provided with a second supply voltage greater than the first supply voltage.
Abstract:
Uplink diversity and interband uplink carrier aggregation in front-end architecture. In some embodiments, a radio-frequency (RF) front-end architecture can include a first transmit/receive (Tx/Rx) front-end system configured to operate with a first antenna, and a second Tx/Rx front-end system configured to operate with a second antenna. The second Tx/Rx front-end system can be a substantial duplicate of the first Tx/Rx front-end system to provide, for example, uplink (UL) diversity functionality and UL multiple-input-and-multiple-output (MIMO) functionality.
Abstract:
Parasitic compensation for radio-frequency (RF) switch applications. In some embodiments, a switching architecture can include a switch network having one or more switchable RF signal paths, where each path contributes to a parasitic effect associated with the switch network. The switching architecture can further include a parasitic compensation circuit coupled to a node of the switch network. The parasitic compensation circuit can be configured to compensate for the parasitic effect of the switch network. In some embodiments, the parasitic compensation circuit can be configured to provide adjustable compensation for the parasitic effect of the switch network.
Abstract:
Temperature compensated circuits for radio-frequency (RF) devices. In some embodiments, an RF circuit can include an input node and a plurality of components interconnected to the input node and configured to yield an impedance for an RF signal at the input node. At least one of the plurality of components can be configured to have temperature-dependence within a temperature range so that the impedance varies to compensate for an effect of temperature change. Such an RF circuit can be, for example, an impedance matching circuit implemented at an output of a power amplifier. The component having temperature-dependence can include a temperature-dependent capacitor such as a ceramic capacitor.
Abstract:
Microelectromechanical systems (MEMS) having contaminant control features. In some embodiments, a MEMS die can include a substrate and an electromechanical assembly implemented on the substrate. The MEMS die can further include a contaminant control component implemented relative to the electromechanical assembly. The contaminant control component can be configured to move contaminants relative to the electromechanical assembly. For example, such contaminants can be moved away from the electromechanical assembly.
Abstract:
Disclosed are devices and methods related to laminated polymeric planar magnetics. In some embodiments, a magnetic device can have a base layer including a polymeric laminate layer. The base layer can further include a set of one or more conductive ribbons implemented on a first side of the polymeric laminate layer. The base layer can have a perimeter that includes at least one cut edge. The magnetic device can further include a structure implemented on the base layer. The structure can include a set of one or more conductor features implemented on a side away from the base layer. The structure can have a perimeter that includes an edge set inward from the cut edge by an amount sufficient to allow a cutting operation that cuts the polymeric laminate layer to yield the cut edge.