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    SUB-BLOCK PROGRAMMING MODE WITH MULTI-TIER BLOCK
    1.
    发明申请
    SUB-BLOCK PROGRAMMING MODE WITH MULTI-TIER BLOCK 审中-公开

    公开(公告)号：WO2023033882A1

    公开(公告)日：2023-03-09

    申请号：PCT/US2022/028236

    申请日：2022-05-08

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： LIEN, Yu-Chung ,  YUAN, Jiahui ,  ELIASH, Tomer

    IPC: G11C16/16 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  H01L27/11529

    Abstract: Apparatuses and techniques are described for programming a multi-tier block in which sub-blocks are arranged in respective tiers. When a program operation involves the source-side sub-block, the NAND strings are pre-charged from the source line. When a program operation involves the drain-side sub-block, the NAND strings are pre-charged from the bit line. When a program operation involves an interior sub-block, the NAND strings can be pre-charged from the bit line if all sub-blocks on the drain side of the interior sub-block are erased, or from the source line if all sub-blocks on the source side of the interior sub-block are erased. A table can be provided which identifies free blocks, free sub-blocks and a corresponding program order. If such a table is not available, the sub-blocks can be read to determine whether they are programmed.

    NON-VOLATILE MEMORY WITH EFFICIENT TESTING DURING ERASE
    2.
    发明申请
    NON-VOLATILE MEMORY WITH EFFICIENT TESTING DURING ERASE 审中-公开

    公开(公告)号：WO2023022767A1

    公开(公告)日：2023-02-23

    申请号：PCT/US2022/028225

    申请日：2022-05-07

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： PACHAMUTHU, Jayavel ,  SUBRAMANIAN, Ramkumar

    IPC: G11C16/34 ,  G11C16/14 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04

    Abstract: A non-volatile memory system erasing groups of connected memory cells separately performs erase verify for memory cells connected to even word lines to generate even results and erase verify for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine if the erase verify process indicates that the erasing has successful completed. In addition, for each group of connected memory cells, a last even result for the group is compared to a last odd result for the group. Even if the erase verify indicated that the erasing has successfully completed, the system may determine that the erasing failed (i.e. due to a defect) if the number of groups of connected memory cells that have the last even result different than the last odd result is greater than a limit.

    FOGGY-FINE PROGRAMMING FOR MEMORY CELLS WITH REDUCED NUMBER OF PROGRAM PULSES
    3.
    发明申请
    FOGGY-FINE PROGRAMMING FOR MEMORY CELLS WITH REDUCED NUMBER OF PROGRAM PULSES 审中-公开

    公开(公告)号：WO2023014413A1

    公开(公告)日：2023-02-09

    申请号：PCT/US2022/027541

    申请日：2022-05-04

    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

    Inventor： WANG, Ming ,  LI, Liang ,  LI, Bruce ,  LI, Will ,  WANG, Yichen

    IPC: G11C16/34 ,  G11C16/24

    Abstract: Apparatuses and techniques are described for programming memory cells with a reduced number of program pulses. A program operation includes a first, foggy program pass followed by a second, fine program pass. The number of program loops in the foggy program pass is minimized while providing relatively narrow Vth distributions for the foggy states. The program loops include one or more checkpoint program loops in which a program speed of the memory cells is determined through a read operation. In a next program loop, the fast-programming memory cells are inhibited from programming while the slow-programming memory cells are programmed with a reduced speed by applying a program speed-reducing bit line voltage. This brings the threshold voltage of the slow-programming memory cells into alignment with the threshold voltage of the fast-programming memory cells.

    CONTROLLING WORD LINE VOLTAGES TO REDUCE READ DISTURB IN A MEMORY DEVICE
    6.
    发明申请
    CONTROLLING WORD LINE VOLTAGES TO REDUCE READ DISTURB IN A MEMORY DEVICE 审中-公开

    公开(公告)号：WO2022093320A1

    公开(公告)日：2022-05-05

    申请号：PCT/US2021/033723

    申请日：2021-05-21

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： ZAINUDDIN, Abu Naser ,  CHIN, Henry ,  YUAN, Jiahui

    IPC: G11C16/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/30 ,  G11C8/08

    Abstract: Apparatuses and techniques are described for reducing read disturb in a memory device by reducing the channel gradient and the charge injection to the memory cell. Channels of unselected NAND strings are boosted before reading memory cells in selected NAND strings. The boosting involves applying a positive voltage to source ends and drain ends of the unselected NAND strings, while drain-side select gate transistors are turned on and then off and a voltage signal of non-adjacent word lines of a selected word line, WLn, increases to a read pass voltage. A voltage signal of adjacent word lines of WLn is increased to a peak level to increase the channel conduction for faster read, where the peak level is less than the read pass voltage, decreased to a reduced level to reduce a channel gradient and therefore reduce a read disturb, then increased to the read pass voltage.

    READ TIME REDUCTION WITH P-WELL BIAS IN MEMORY DEVICE
    7.
    发明申请
    READ TIME REDUCTION WITH P-WELL BIAS IN MEMORY DEVICE 审中-公开

    公开(公告)号：WO2022046219A1

    公开(公告)日：2022-03-03

    申请号：PCT/US2021/033720

    申请日：2021-05-21

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： ZAINUDDIN, Abu Naser ,  KWON, Ohwon ,  YUAN, Jiahui

    IPC: G11C16/26 ,  G11C16/30 ,  G11C16/04 ,  G11C16/24 ,  H01L27/11529 ,  H01L27/11582

    Abstract: Apparatuses and techniques are described for reducing read time in a memory device. A source voltage signal, Vcelsrc, and a body voltage signal, Vp-well, of a source region and a p-well, respectively, of a substrate of a NAND string are controlled to reduce the channel resistance. Vcelsrc can be temporarily reduced, e.g., provided with a negative voltage kick, while Vp-well is non-decreasing during a read operation. The negative voltage kick decreases a body bias of the NAND string in its channel to reduce the channel resistance and increase the current. The negative voltage kick can be initiated when a bit line clamp transistor is made conductive to allow a current to flow in the NAND string. The magnitude and duration of the negative voltage kick can be adjusted based on various factors.

    MEMORY BLOCK WITH SEPARATELY DRIVEN SOURCE REGIONS TO IMPROVE PERFORMANCE
    8.
    发明申请
    MEMORY BLOCK WITH SEPARATELY DRIVEN SOURCE REGIONS TO IMPROVE PERFORMANCE 审中-公开

    公开(公告)号：WO2022039813A1

    公开(公告)日：2022-02-24

    申请号：PCT/US2021/033706

    申请日：2021-05-21

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： CUI, Zhixin ,  GAUTAM, Rajdeep ,  CHIBVONGODZE, Hardwell

    IPC: H01L27/11519 ,  H01L27/11565 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11521 ,  G11C16/04

    Abstract: Apparatuses and techniques are described for providing separate source regions in the substrate below a block of memory cells. The source regions can be separately driven by respective voltage drivers to provide benefits such as more uniform program and erase speeds and narrower threshold voltage distributions. In one approach, a single source region is provided and divided into multiple source regions by etching trenches and filling the trenches with an insulating material. Contacts to the source regions can include post-shaped contacts which extend through the block for each source region. In another approach, one or more planar contacts extend through the block for each source region. In another aspect, a program operation applies different voltages to the respective source regions during a verify test of a program operation.

    HYBRID ERASE MODE FOR HIGH DATA RETENTION IN MEMORY DEVICE
    9.
    发明申请
    HYBRID ERASE MODE FOR HIGH DATA RETENTION IN MEMORY DEVICE 审中-公开

    公开(公告)号：WO2021257129A1

    公开(公告)日：2021-12-23

    申请号：PCT/US2021/018002

    申请日：2021-02-12

    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

    Inventor： WANG, Ming ,  LI, Liang ,  WAN, Jun

    IPC: G11C11/56 ,  G11C16/14 ,  G11C16/34 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3445 ,  G11C16/349 ,  H01L27/11565 ,  H01L27/11582

    Abstract: Apparatuses and techniques are described for performing an erase operation for a set of memory cells, where the erase operation includes an all word line erase phase to save time followed by an odd-even word line erase phase to improve data retention. A transition to the odd-even word line erase phase can be triggered when the memory cells pass a first verify test which indicates that the threshold voltages of the memory cells have decreased below a first voltage. Or, the transition can be triggered when a threshold number of erase-verify iterations have been performed. The erase operation may be completed when the memory cells pass a second verify test which indicates that the threshold voltages of the memory cells have decreased below a second voltage which is less than the first voltage.

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