公开(公告)号：WO2008094714A1

公开(公告)日：2008-08-07

申请号：PCT/US2008/050009

申请日：2008-01-02

Applicant: FREESCALE SEMICONDUCTOR INC. ,  CARPENTER, Burton J. ,  LANGFORD, Patrice L. ,  LINDSAY, Wayne S. ,  LOW, Boon Yew

Inventor： CARPENTER, Burton J. ,  LANGFORD, Patrice L. ,  LINDSAY, Wayne S. ,  LOW, Boon Yew

IPC: H05K1/00 ,  H01L23/28 ,  H01R12/00

CPC classification number: H05K3/3436 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K3/3452 ,  H05K2201/094 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A packaging assembly (29), such as a ball grid array package, is formed to reduce the effects of warpage by varying the size of solder ball aperture openings in the solder mask layer so that smaller solder ball aperture openings are located on the carrier substrate (20) areas where warpage is higher and larger solder ball aperture openings are located on the carrier substrate where warpage is lower.

Abstract translation: 形成诸如球栅阵列封装的封装组件（29），以通过改变焊料掩模层中的焊球孔开口的尺寸来减小翘曲的影响，使得较小的焊球开口开口位于载体衬底上 （20）翘曲程度较高的焊球开口位于翘曲较低的载体基板上。

公开(公告)号：WO2007136932A3

公开(公告)日：2009-03-26

申请号：PCT/US2007065619

申请日：2007-03-30

Applicant: FREESCALE SEMICONDUCTOR INC ,  TRAN TU-ANH N ,  VO NHAT D ,  CARPENTER BURTON J ,  HONG DAE Y ,  MILLER JAMES W ,  PHILLIPS KENDALL D

Inventor： TRAN TU-ANH N ,  VO NHAT D ,  CARPENTER BURTON J ,  HONG DAE Y ,  MILLER JAMES W ,  PHILLIPS KENDALL D

IPC: H01L23/52

CPC classification number: H01L27/0203 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05552 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06051 ,  H01L2224/06153 ,  H01L2224/06159 ,  H01L2224/48463 ,  H01L2224/49431 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A pad (20) is electrically connected to a first I/O cell (14) while also physically overlying active circuitry of a second I/O cell (16). Note that although the pad (20) overlies the second I/O cell (16), the pad (20) is not electrically connected to the I/O cell (16). Such a pattern may be replicated in any desired manner so that the I/O cells (e.g. 300-310) may have a finer pitch than the corresponding pads (320-324 and 330-335). In addition, the size of the pads may be increased (e.g. pad 131 may be bigger than pad 130) while the width "c" of the I/O cells (132-135) does not have to be increased. Such a pattern (e.g. 500) may be arranged so that the area required in one or more dimensions may be minimized.

Abstract translation: 垫（20）电连接到第一I / O单元（14），同时物理地覆盖第二I / O单元（16）的有源电路。 注意，虽然焊盘（20）覆盖第二I / O单元（16），但是焊盘（20）不与I / O单元（16）电连接。 这样的图案可以以任何期望的方式复制，使得I / O单元（例如300-310）可以具有比相应的垫（320-324和330-335）更细的间距。 此外，可以增加焊盘的尺寸（例如焊盘131可能大于焊盘130），而不必增加I / O单元（132-135）的宽度“c”。 这种图案（例如500）可以被布置成使得在一个或多个维度中所需的区域可以被最小化。

公开(公告)号：WO2007136932A2

公开(公告)日：2007-11-29

申请号：PCT/US2007/065619

申请日：2007-03-30

Applicant: FREESCALE SEMICONDUCTOR INC. ,  TRAN, Tu-Anh N. ,  VO, Nhat D. ,  CARPENTER, Burton J. ,  HONG, Dae Y. ,  MILLER, James W. ,  PHILLIPS, Kendall D.

Inventor： TRAN, Tu-Anh N. ,  VO, Nhat D. ,  CARPENTER, Burton J. ,  HONG, Dae Y. ,  MILLER, James W. ,  PHILLIPS, Kendall D.

IPC: H01L23/52 ,  H01L23/48

CPC classification number: H01L27/0203 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05552 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06051 ,  H01L2224/06153 ,  H01L2224/06159 ,  H01L2224/48463 ,  H01L2224/49431 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A pad (20) is electrically connected to a first I/O cell (14) while also physically overlying active circuitry of a second I/O cell (16). Note that although the pad (20) overlies the second I/O cell (16), the pad (20) is not electrically connected to the I/O cell (16). Such a pattern may be replicated in any desired manner so that the I/O cells (e.g. 300-310) may have a finer pitch than the corresponding pads (320-324 and 330-335). In addition, the size of the pads may be increased (e.g. pad 131 may be bigger than pad 130) while the width "c" of the I/O cells (132-135) does not have to be increased. Such a pattern (e.g. 500) may be arranged so that the area required in one or more dimensions may be minimized.

Abstract translation: 垫（20）电连接到第一I / O单元（14），同时物理地覆盖第二I / O单元（16）的有源电路。 注意，虽然焊盘（20）覆盖第二I / O单元（16），但是焊盘（20）不与I / O单元（16）电连接。 这样的图案可以以任何期望的方式复制，使得I / O单元（例如300-310）可以具有比相应的垫（320-324和330-335）更细的间距。 此外，可以增加焊盘的尺寸（例如焊盘131可能大于焊盘130），而不必增加I / O单元（132-135）的宽度“c”。 可以布置这样的图案（例如500），使得在一个或多个维度中所需的区域可以被最小化。