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    ELECTRONIC DEVICE INCLUDING INSULATING LAYERS HAVING DIFFERENT STRAINS AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE
    1.
    发明申请
    ELECTRONIC DEVICE INCLUDING INSULATING LAYERS HAVING DIFFERENT STRAINS AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE 审中-公开
    包括具有不同应变的绝缘层的电子器件和用于形成电子器件的工艺

    公开(公告)号：WO2008094745A1

    公开(公告)日：2008-08-07

    申请号：PCT/US2008/050969

    申请日：2008-01-14

    Applicant: FREESCALE SEMICONDUCTOR INC. ,  GRUDOWSKI, Paul, A. ,  KOLAGUNTA, Venkat, R. ,  SHROFF, Mehul, D.

    Inventor： GRUDOWSKI, Paul, A. ,  KOLAGUNTA, Venkat, R. ,  SHROFF, Mehul, D.

    IPC: H01L21/76

    CPC classification number: H01L27/1203 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/3143 ,  H01L21/3185 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/78 ,  H01L29/7843

    Abstract: An electronic device can include a field isolation region (22) and a first insulating layer (42) having a first strain and having a portion (421), which from a top view, lies entirely within the field isolation region (22). The electronic device can also include a second insulating layer (72) having a second strain different from the first strain and including an opening. From a top view, the portion (421) of the first insulating layer (72) can lie within the opening in the second insulating layer (72). In one embodiment, the field isolation region (22) can include a dummy structure (241) and the portion of the first insulating layer (421) can overlie the dummy structure (241). A process of forming the electronic device can include forming an island portion (421) of an insulating layer (72) wherein from a top view, the island portion (421) lies entirely within the field isolation region (22).

    Abstract translation: 电子设备可以包括场隔离区域（22）和具有第一应变的第一绝缘层（42），并具有从顶视图完全位于场隔离区域（22）内的部分（421）。 电子设备还可以包括具有不同于第一应变的第二应变并且包括开口的第二绝缘层（72）。 从顶部看，第一绝缘层（72）的部分（421）可以位于第二绝缘层（72）的开口内。 在一个实施例中，场隔离区域（22）可以包括虚拟结构（241），并且第一绝缘层（421）的部分可以覆盖虚拟结构（241）。 形成电子器件的方法可以包括形成绝缘层（72）的岛部（421），其中从顶视图，岛部（421）完全位于场隔离区（22）内。

    SEMICONDUCTOR PROCESS INTEGRATING SOURCE/DRAIN STRESSORS AND INTERLEVEL DIELECTRIC LAYER STRESSORS
    2.
    发明申请
    SEMICONDUCTOR PROCESS INTEGRATING SOURCE/DRAIN STRESSORS AND INTERLEVEL DIELECTRIC LAYER STRESSORS 审中-公开
    半导体工艺整合源/排水压力机和交互式电介质层压机

    公开(公告)号：WO2007103609A2

    公开(公告)日：2007-09-13

    申请号：PCT/US2007/061841

    申请日：2007-02-08

    Applicant: FREESCALE SEMICONDUCTOR INC. ,  ZHANG, Da ,  ADAMS, Vance H. ,  NGUYEN, Bich-Yen ,  GRUDOWSKI, Paul A.

    Inventor： ZHANG, Da ,  ADAMS, Vance H. ,  NGUYEN, Bich-Yen ,  GRUDOWSKI, Paul A.

    IPC: H01L21/336

    CPC classification number: H01L29/7846 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78654

    Abstract: A semiconductor fabrication process includes forming isolation structures (106) on either side of a transistor region, forming a gate structure (110) overlying the transistor region, removing source/drain regions (107) to form source/drain recesses (120), removing portions of the isolation structures to form recessed isolation structures (126), and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor (140) is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor. The ILD stressor is preferably compressive or tensile silicon nitride and the source/drain structure is preferably silicon germanium or silicon carbon.

    Abstract translation: 半导体制造工艺包括在晶体管区域的任一侧上形成隔离结构（106），形成覆盖晶体管区域的栅极结构（110），去除源极/漏极区域（107）以形成源极/漏极凹部（120），去除 隔离结构的部分以形成凹陷的隔离结构（126），并且用诸如外延形成的半导体的源极/漏极应力源填充源/漏极凹部。 源极/漏极凹部的下表面优选比凹陷隔离结构的上表面深大约10至30nm。 填充源极/漏极凹部可以在形成凹入的隔离结构之前或之后。 然后将ILD应激源（140）沉积在晶体管区域上，使得ILD应力源与源极/漏极结构的侧壁相邻，从而将ILD应力源耦合到源极/漏极应力源。 ILD应力器优选为压缩或拉伸氮化硅，并且源极/漏极结构优选为硅锗或硅碳。

    SEMICONDUCTOR PROCESS INTEGRATING SOURCE/DRAIN STRESSORS AND INTERLEVEL DIELECTRIC LAYER STRESSORS
    3.
    发明申请
    SEMICONDUCTOR PROCESS INTEGRATING SOURCE/DRAIN STRESSORS AND INTERLEVEL DIELECTRIC LAYER STRESSORS 审中-公开
    半导体工艺整合源/排水压力机和交互式电介质层压机

    公开(公告)号：WO2007103609A3

    公开(公告)日：2008-12-31

    申请号：PCT/US2007061841

    申请日：2007-02-08

    Applicant: FREESCALE SEMICONDUCTOR INC ,  ZHANG DA ,  ADAMS VANCE H ,  NGUYEN BICH-YEN ,  GRUDOWSKI PAUL A

    Inventor： ZHANG DA ,  ADAMS VANCE H ,  NGUYEN BICH-YEN ,  GRUDOWSKI PAUL A

    IPC: H01L21/336

    CPC classification number: H01L29/7846 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78654

    Abstract: A semiconductor fabrication process includes forming isolation structures (106) on either side of a transistor region, forming a gate structure (110) overlying the transistor region, removing source/drain regions (107) to form source/drain recesses (120), removing portions of the isolation structures to form recessed isolation structures (126), and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor (140) is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor. The ILD stressor is preferably compressive or tensile silicon nitride and the source/drain structure is preferably silicon germanium or silicon carbon.

    Abstract translation: 半导体制造工艺包括在晶体管区域的任一侧上形成隔离结构（106），形成覆盖晶体管区域的栅极结构（110），去除源极/漏极区域（107）以形成源极/漏极凹部（120），去除 隔离结构的部分以形成凹陷的隔离结构（126），并且用诸如外延形成的半导体的源极/漏极应力源填充源/漏极凹部。 源极/漏极凹部的下表面优选比凹陷隔离结构的上表面深大约10至30nm。 填充源极/漏极凹部可以在形成凹入的隔离结构之前或之后。 然后将ILD应激源（140）沉积在晶体管区域上，使得ILD应力源与源极/漏极结构的侧壁相邻，从而将ILD应力源耦合到源极/漏极应力源。 ILD应力器优选为压缩或拉伸氮化硅，并且源极/漏极结构优选为硅锗或硅碳。

    METHOD OF FORMING AN ELECTRONIC DEVICE
    5.
    发明申请
    METHOD OF FORMING AN ELECTRONIC DEVICE 审中-公开
    形成电子设备的方法

    公开(公告)号：WO2006107414A3

    公开(公告)日：2007-04-26

    申请号：PCT/US2006005370

    申请日：2006-02-16

    Applicant: FREESCALE SEMICONDUCTOR INC ,  LIM SANGWOO ,  GRUDOWSKI PAUL A ,  JAHANBANI MOHAMAD M ,  TSENG HSING H ,  YEAP CHOH-FEI

    Inventor： LIM SANGWOO ,  GRUDOWSKI PAUL A ,  JAHANBANI MOHAMAD M ,  TSENG HSING H ,  YEAP CHOH-FEI

    IPC: H01L21/8234

    CPC classification number: H01L21/823462

    Abstract: A method of forming an electronic device (100) includes etching a portion of a first gate dielectric layer (104) to reduce a thickness of the gate dielectric layer (304) within that portion. In one embodiment, portions not being etched may be covered by mask (206). In another embodiment, different portions may be etched during different times to give different thicknesses for the first gate dielectric layer. In a particular embodiment, a second gate dielectric layer (402) may be formed over the first gate dielectric layer (104, 504, 304) after etching the portion. The second gate dielectric layer (402) can have a dielectric constant greater than the dielectric constant of the first gate dielectric layer (104, 504. 304). Subsequent gate electrode (606) and source/drain region formation can be performed to form a transistor structure (20, 22, 24).

    Abstract translation: 形成电子器件（100）的方法包括蚀刻第一栅极介电层（104）的一部分以减小该部分内的栅极电介质层（304）的厚度。 在一个实施例中，未被蚀刻的部分可以被掩模（206）覆盖。 在另一个实施例中，不同部分可以在不同时间被蚀刻，以给予第一栅极介电层不同的厚度。 在特定实施例中，在蚀刻该部分之后，可以在第一栅极介电层（104,504,304）之上形成第二栅极电介质层（402）。 第二栅极介电层（402）可以具有大于第一栅极介电层（104,504304）的介电常数的介电常数。 可以执行随后的栅电极（606）和源极/漏极区域形成以形成晶体管结构（20,22,24）。

    SEMICONDUCTOR DEVICE WITH STRESSORS AND METHODS THEREOF
    6.
    发明申请
    SEMICONDUCTOR DEVICE WITH STRESSORS AND METHODS THEREOF 审中-公开
    具有抗压件的半导体器件及其方法

    公开(公告)号：WO2008147608A1

    公开(公告)日：2008-12-04

    申请号：PCT/US2008/061268

    申请日：2008-04-23

    Applicant: FREESCALE SEMICONDUCTOR INC. ,  ZOLLNER, Stefan ,  DHANDAPANI, Veeraraghavan ,  GRUDOWSKI, Paul A.

    Inventor： ZOLLNER, Stefan ,  DHANDAPANI, Veeraraghavan ,  GRUDOWSKI, Paul A.

    IPC: H01L21/336 ,  H01L29/78

    CPC classification number: H01L29/66628 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/66772 ,  H01L29/7843

    Abstract: A semiconductor device (10) is formed in a semiconductor layer (16). A gate dielectric (20) is formed over a top surface of the semiconductor layer (16). A gate stack (18) is over the gate dielectric (20). A sidewall spacer (24) is formed around the gate stack (18). Using the sidewall spacer (24) as a mask, an implant is performed to form deep source/drain regions (28, 30) in the semiconductor layer. Silicon carbon regions (32, 36, 34) are formed on the deep source/drain regions (28, 30) and a top surface of the gate stack. The silicon carbon regions (32, 34, 36) are silicided with nickel.

    Abstract translation: 半导体器件（10）形成在半导体层（16）中。 栅电介质（20）形成在半导体层（16）的顶表面上。 栅极堆叠（18）位于栅极电介质（20）的上方。 在栅极堆叠（18）周围形成侧壁间隔物（24）。 使用侧壁间隔件（24）作为掩模，执行注入以在半导体层中形成深源极/漏极区域（28,30）。 在深源/漏区（28,30）和栅叠层的顶表面上形成硅碳区（32,36,34）。 硅碳区域（32,34,36）用镍硅化。

    ELECTRONIC DEVICE INCLUDING A TRANSISTOR STRUCTURE HAVING AN ACTIVE REGION ADJACENT TO A STRESSOR LAYER AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE
    7.
    发明申请
    ELECTRONIC DEVICE INCLUDING A TRANSISTOR STRUCTURE HAVING AN ACTIVE REGION ADJACENT TO A STRESSOR LAYER AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE 审中-公开
    包括具有与激励区邻近的晶体管结构的电子器件以及形成电子器件的工艺

    公开(公告)号：WO2007055853A2

    公开(公告)日：2007-05-18

    申请号：PCT/US2006039650

    申请日：2006-10-10

    Applicant: FREESCALE SEMICONDUCTOR INC ,  ADAMS VANCE H ,  GRUDOWSKI PAUL A ,  KOLAGUNTA VENKAT R ,  WINSTEAD BRIAN A

    Inventor： ADAMS VANCE H ,  GRUDOWSKI PAUL A ,  KOLAGUNTA VENKAT R ,  WINSTEAD BRIAN A

    IPC: H01L29/792

    CPC classification number: H01L21/84 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7843

    Abstract: An electronic device (10) can include a transistor structure (50) of a first conductivity type, a field isolation region (22), and a layer (130) of a first stress type overlying the field isolation region. For example, the transistor structure (50) may be a p-channel transistor structure (50) and the first stress type may be tensile, or the transistor structure (60) may be an n- channel transistor structure and the first stress type (70) may be compressive. The transistor structure (50) can include a channel region (54) that lies within an active region. An edge of the active region includes the interface between the channel region (54) and the field isolation region (22). From a top view, the layer can include an edge that lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region (54) of the transistor structure (50).

    Abstract translation: 电子器件（10）可以包括第一导电类型的晶体管结构（50），场隔离区（22）以及覆盖场隔离区的第一应力类型的层（130）。 例如，晶体管结构（50）可以是p沟道晶体管结构（50），并且第一应力类型可以是拉伸的，或者晶体管结构（60）可以是n沟道晶体管结构并且第一应力类型 70）可能是压缩的。 晶体管结构（50）可以包括位于有源区内的沟道区（54）。 有源区的边缘包括沟道区（54）和场隔离区（22）之间的界面。 从顶视图看，该层可以包括位于有源区边缘附近的边缘。 边缘之间的位置关系会影响晶体管结构（50）的沟道区（54）内的载流子迁移率。

    SEMICONDUCTOR DEVICE HAVING STRESSORS AND METHOD FOR FORMING
    9.
    发明申请
    SEMICONDUCTOR DEVICE HAVING STRESSORS AND METHOD FOR FORMING 审中-公开
    具有应力的半导体器件和形成方法

    公开(公告)号：WO2007097814A3

    公开(公告)日：2008-10-09

    申请号：PCT/US2006060638

    申请日：2006-11-08

    Applicant: FREESCALE SEMICONDUCTOR INC ,  SHROFF MEHUL D ,  GRUDOWSKI PAUL A

    Inventor： SHROFF MEHUL D ,  GRUDOWSKI PAUL A

    IPC: H01L21/335 ,  H01L27/088

    CPC classification number: H01L21/823807 ,  H01L21/3185 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/823864 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7843

    Abstract: N channel (113, 115) and P channel (111) transistors are enhanced by applying stressor layers of tensile (128) and compressive (126), respectively, over them. A previously unknown problem was discovered concerning the two stressor layers, which both may conveniently be nitride but made somewhat differently. The two stressors have different etch rates which results in deleterious effects when etching a contact hole at the interface between the two stressors. A contact to a gate is often preferably half way between N and P channel transistors which is also the seemingly best location for the border between the two stressor layers. The contact etch at the border can result in pitting of the underlying gate structure or in residual nitride in the contact hole. Therefore, it has been found beneficial to ensure that each contact (154) is at least some predetermined distance from the stressor of the opposite type from the one the contact is passing through.

    Abstract translation: 通过分别在其上施加拉伸（128）和压缩（126）的应力层，增强了N沟道（113,115）和P沟道（111）晶体管。 发现关于两个应力层的以前未知的问题，这两个应力层都可以方便地是氮化的，但是略有不同。 两个应力源具有不同的蚀刻速率，这在蚀刻两个应激物之间的界面处的接触孔时会产生有害影响。 与栅极的接触通常优选地在N沟道晶体管和P沟道晶体管之间的中间，这也是两个应力层之间边界看似最好的位置。 在边界处的接触蚀刻可导致底层栅极结构或接触孔中的残余氮化物的点蚀。 因此，已经发现有益的是确保每个接触件（154）与接触件通过的相反类型的应力器至少一定的距离。

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