公开(公告)号：WO2012158424A2

公开(公告)日：2012-11-22

申请号：PCT/US2012037072

申请日：2012-05-09

Applicant: MICRON TECHNOLOGY INC ,  ROCKLEIN MATTHEW N ,  RAMASWAMY D V NIRMAL

Inventor： ROCKLEIN MATTHEW N ,  RAMASWAMY D V NIRMAL

CPC classification number: H01L45/146 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1675

Abstract: Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell (106, 230, 350, 360, 470, 480) are provided. One example method of a resistive memory cell (106, 230, 350, 360, 470, 480) can include a number of dielectric regions (236, 356, 366, 476, 486) formed between two electrodes (102/104, 232/234, 352/354, 362/364, 472/474, 482/484), and a barrier dielectric region (238, 358, 368, 478, 488) formed between each of the dielectric regions (236, 356, 366, 476, 486). The barrier dielectric region (238, 358, 368, 478, 488) serves to reduce an oxygen diffusion rate associated with the dielectric regions (236, 356, 366, 476, 486).

Abstract translation: 提供了半导体存储器件，电阻存储器件，存储器单元结构以及形成电阻存储单元（106,230,350,360,470,480）的方法。 电阻存储器单元（106,230,350,360,470,480）的一个示例性方法可以包括形成在两个电极（102 / 104,232和486）之间的多个电介质区域（236,356,366,476,468） 234,352 / 354,462 / 364,472 / 474,482 / 484）和形成在每个介电区域（236,356,366,476）之间的势垒电介质区域（238,358,368,478,468） ，486）。 势垒电介质区域（238,358,368,478,448）用于降低与电介质区域（236,356,366,476,468）相关的氧扩散速率。

公开(公告)号：WO2011152858A2

公开(公告)日：2011-12-08

申请号：PCT/US2011/000971

申请日：2011-05-27

Applicant: MICRON TECHNOLOGY, INC. ,  RAMASWAMY, D., V., Nirmal ,  SANDHU, Gurtej, S.

Inventor： RAMASWAMY, D., V., Nirmal ,  SANDHU, Gurtej, S.

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: G11C13/0007 ,  G11C2213/55 ,  G11C2213/56 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616

Abstract: Methods, devices, and systems associated with oxide based memory are described herein. In one or more embodiments, a method of forming an oxide based memory cell includes forming a first electrode, forming a tunnel barrier, wherein a first portion of the tunnel barrier includes a first material and a second portion of the tunnel barrier includes a second material, forming an oxygen source, and forming a second electrode.

Abstract translation: 本文描述了与基于氧化物的存储器相关联的方法，设备和系统。 在一个或多个实施例中，形成基于氧化物的存储单元的方法包括形成第一电极，形成隧道势垒，其中隧道势垒的第一部分包括第一材料，隧道势垒的第二部分包括第二材料 ，形成氧源，形成第二电极。

公开(公告)号：WO2011119424A2

公开(公告)日：2011-09-29

申请号：PCT/US2011/028954

申请日：2011-03-18

Applicant: MICRON TECHNOLOGY, INC. ,  RAMASWAMY, D., V., Nirmal ,  ROCKLEIN, Matthew, N. ,  BREWER, Rhett

Inventor： RAMASWAMY, D., V., Nirmal ,  ROCKLEIN, Matthew, N. ,  BREWER, Rhett

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/28282 ,  B82Y10/00 ,  G11C11/5671 ,  H01L21/02148 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/42348

Abstract: Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel dielectric and a protective film over the nanodots. In another memory cell, the charge storage node includes nanodots that include a ruthenium alloy. Memory cells can include an inter gate dielectric over the protective film or ruthenium alloy nanodots and a control gate over the inter gate dielectric. The protective film and ruthenium alloy can be configured to protect at least some of the nanodots from vaporizing during formation of the inter gate dielectric.

Abstract translation: 公开了用于形成存储器单元的存储器，系统和方法。 一个这种存储单元包括电荷存储节点，其在隧道电介质上方包括纳米点，并且在纳米点上包括保护膜。 在另一个存储单元中，电荷存储节点包括包含钌合金的纳米点。 存储器单元可以包括在保护膜或钌合金纳米点上的栅极间电介质和栅极间电介质上的控制栅极。 保护膜和钌合金可以被配置为在形成栅极间电介质期间保护至少一些纳米点不被蒸发。

公开(公告)号：WO2010080318A3

公开(公告)日：2010-09-23

申请号：PCT/US2009067387

申请日：2009-12-09

Applicant: MICRON TECHNOLOGY INC ,  RAMASWAMY D V NIRMAL ,  ROCKLEIN NOEL ,  MIN KYU S

Inventor： RAMASWAMY D V NIRMAL ,  ROCKLEIN NOEL ,  MIN KYU S

IPC: H01L21/31 ,  H01L21/8247 ,  H01L27/115

CPC classification number: H01L29/7881 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultrahigh k dielectric material over the charge -retaining region, and a control gate material over the crystalline ultra-high k dielectric material. Additionally, the memory cells may include an amorphous region between the charge -retaining region and the crystalline ultra-high k dielectric material, and/or may include an amorphous region between the crystalline ultra-high k dielectric material and the control gate material. Some embodiments include methods of forming memory cells which contain an amorphous region between a charge-retaining region and a crystalline ultra-high k dielectric material, and/or which contain an amorphous region between a crystalline ultra-high k dielectric material and a control gate material.

Abstract translation: 一些实施例包括存储单元。 存储器单元可以包括隧道电介质材料，隧道电介质材料上的电荷保留区域，电荷保留区域上方的晶体超高k电介质材料以及晶体超高k电介质材料上的控制栅极材料。 另外，存储器单元可以包括在电荷保持区和晶体超高k电介质材料之间的非晶区，和/或可以包括在晶体超高k电介质材料和控制栅材料之间的非晶区。 一些实施例包括形成存储器单元的方法，所述存储器单元包含电荷保持区和晶体超高k电介质材料之间的非晶区，和/或在晶体超高k电介质材料和控制栅之间包含非晶区 材料。

公开(公告)号：WO2010080318A2

公开(公告)日：2010-07-15

申请号：PCT/US2009/067387

申请日：2009-12-09

Applicant: MICRON TECHNOLOGY, INC. ,  RAMASWAMY, D., V., Nirmal ,  ROCKLEIN, Noel ,  MIN, Kyu, S.

Inventor： RAMASWAMY, D., V., Nirmal ,  ROCKLEIN, Noel ,  MIN, Kyu, S.

IPC: H01L21/31 ,  H01L27/115 ,  H01L21/8247

CPC classification number: H01L29/7881 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultrahigh k dielectric material over the charge -retaining region, and a control gate material over the crystalline ultra-high k dielectric material. Additionally, the memory cells may include an amorphous region between the charge -retaining region and the crystalline ultra-high k dielectric material, and/or may include an amorphous region between the crystalline ultra-high k dielectric material and the control gate material. Some embodiments include methods of forming memory cells which contain an amorphous region between a charge-retaining region and a crystalline ultra-high k dielectric material, and/or which contain an amorphous region between a crystalline ultra-high k dielectric material and a control gate material.

Abstract translation: 一些实施例包括存储器单元。 存储单元可以包括隧道介电材料，隧道电介质材料上的电荷保持区域，电荷存储区域上的结晶超高电介质材料，以及结晶超高k电介质材料上的控制栅极材料。 另外，存储单元可以包括在电荷存储区域和结晶超高k电介质材料之间的非晶区域，和/或可以包括晶体超高k电介质材料和控制栅极材料之间的非晶区域。 一些实施例包括形成在电荷保持区域和结晶超高k电介质材料之间形成非晶区域的存储单元的方法，和/或在晶体超高k电介质材料和控制栅极之间包含非晶区域的方法 材料。

公开(公告)号：WO2013015934A3

公开(公告)日：2013-04-18

申请号：PCT/US2012044483

申请日：2012-06-27

Applicant: MICRON TECHNOLOGY INC ,  SANDHU GURTEJ S ,  RAMASWAMY D V NIRMAL

Inventor： SANDHU GURTEJ S ,  RAMASWAMY D V NIRMAL

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L29/792 ,  G11C16/0416 ,  G11C16/3418 ,  H01L21/28273 ,  H01L29/788

Abstract: Some embodiments include memory cells which have channel-supporting material, dielectric material over the channel-supporting material, carrier-trapping material over the dielectric material and an electrically conductive electrode material over and directly against the carrier-trapping material; where the carrier-trapping material includes gallium, indium, zinc and oxygen. Some embodiments include methods of storing information. A memory cell to is provided which has a channel-supporting material, a dielectric material over the channel-supporting material, a carrier-trapping material over the dielectric material, and an electrically conductive electrode material over and directly against the carrier-trapping material; where the carrier-trapping material includes gallium, indium, zinc and oxygen. It is determined if carriers are trapped in the carrier-trapping material to thereby ascertain a memory state of the memory cell.

Abstract translation: 一些实施例包括具有通道支撑材料，在通道支撑材料上的电介质材料，介电材料上方的载流子捕获材料以及超过并直接抵靠载体捕获材料的导电电极材料的存储单元; 其中载流子捕获材料包括镓，铟，锌和氧。 一些实施例包括存储信息的方法。 提供一种存储单元，其具有通道支撑材料，在通道支撑材料上方的介电材料，介电材料上的载流子捕获材料，以及在载体捕获材料上方并直接抵靠载体捕获材料的导电电极材料; 其中载流子捕获材料包括镓，铟，锌和氧。 确定载体是否被捕获在载流子捕获材料中，从而确定存储单元的存储状态。

公开(公告)号：WO2011152858A3

公开(公告)日：2012-04-05

申请号：PCT/US2011000971

申请日：2011-05-27

Applicant: MICRON TECHNOLOGY INC ,  RAMASWAMY D V NIRMAL ,  SANDHU GURTEJ S

Inventor： RAMASWAMY D V NIRMAL ,  SANDHU GURTEJ S

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: G11C13/0007 ,  G11C2213/55 ,  G11C2213/56 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616

Abstract: Methods, devices, and systems associated with oxide based memory are described herein. In one or more embodiments, a method of forming an oxide based memory cell includes forming a first electrode, forming a tunnel barrier, wherein a first portion of the tunnel barrier includes a first material and a second portion of the tunnel barrier includes a second material, forming an oxygen source, and forming a second electrode.

Abstract translation: 本文描述了与基于氧化物的存储器相关联的方法，设备和系统。 在一个或多个实施例中，形成基于氧化物的存储单元的方法包括形成第一电极，形成隧道势垒，其中隧道势垒的第一部分包括第一材料，隧道势垒的第二部分包括第二材料 ，形成氧源，形成第二电极。

公开(公告)号：WO2008076152A3

公开(公告)日：2008-08-28

申请号：PCT/US2007017414

申请日：2007-08-03

Applicant: MICRON TECHNOLOGY INC ,  SANDHU GURTEJ S ,  RAMASWAMY D V NIRMAL

Inventor： SANDHU GURTEJ S ,  RAMASWAMY D V NIRMAL

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/06 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L29/788 ,  B82Y10/00 ,  B82Y99/00 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881 ,  Y10S977/721 ,  Y10S977/762

Abstract: A memory cell (100) is provided including a tunnel dielectric layer (104) overlying a semiconductor substrate (102). The memory cell also includes a floating gate having a first portion (106) overlying the tunnel dielectric layer and a second portion (116) in the form of a nanorod extending from the first portion. In addition, a control gate layer (122) is separated from the floating gate by an intergate dielectric layer (120).

Abstract translation: 提供了包括覆盖在半导体衬底（102）上的隧道电介质层（104）的存储单元（100）。 存储单元还包括具有覆盖隧道介电层的第一部分（106）的浮动栅极和从第一部分延伸的纳米棒形式的第二部分（116）。 此外，控制栅极层（122）通过栅极间介电层（120）与浮置栅极分离。

公开(公告)号：WO2012145130A3

公开(公告)日：2013-03-14

申请号：PCT/US2012030904

申请日：2012-03-28

Applicant: MICRON TECHNOLOGY INC ,  RAMASWAMY D V NIRMAL ,  SANDHU GURTEJ S

Inventor： RAMASWAMY D V NIRMAL ,  SANDHU GURTEJ S

IPC: H01L21/328 ,  H01L29/72

CPC classification number: H01L29/872 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/71 ,  H01L27/1021 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/285 ,  H01L29/885 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

Abstract: Methods, devices, and systems are provided for a select device that can include a semiconductive stack of at least one semiconductive material formed on a first electrode, where the semiconductive stack can have a thickness of about 700 angstroms () or less. Each of the at least one semiconductive material can have an associated band gap of about 4 electron volts (eV) or less and a second electrode can be formed on the semiconductive stack.

Abstract translation: 为选择装置提供方法，装置和系统，所述选择装置可以包括形成在第一电极上的至少一个半导体材料的半导体叠层，其中半导体叠层可以具有约700埃（℃）或更小的厚度。 所述至少一个半导体材料中的每一个可以具有约4电子伏（eV）或更小的相关带隙，并且可以在半导体叠层上形成第二电极。

公开(公告)号：WO2011119424A3

公开(公告)日：2012-01-05

申请号：PCT/US2011028954

申请日：2011-03-18

Applicant: MICRON TECHNOLOGY INC ,  RAMASWAMY D V NIRMAL ,  ROCKLEIN MATTHEW N ,  BREWER RHETT

Inventor： RAMASWAMY D V NIRMAL ,  ROCKLEIN MATTHEW N ,  BREWER RHETT

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/28282 ,  B82Y10/00 ,  G11C11/5671 ,  H01L21/02148 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/42348

Abstract: Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel dielectric and a protective film over the nanodots. In another memory cell, the charge storage node includes nanodots that include a ruthenium alloy. Memory cells can include an inter gate dielectric over the protective film or ruthenium alloy nanodots and a control gate over the inter gate dielectric. The protective film and ruthenium alloy can be configured to protect at least some of the nanodots from vaporizing during formation of the inter gate dielectric.

Abstract translation: 公开了用于形成存储器单元的存储器，系统和方法。 一个这种存储单元包括电荷存储节点，其在隧道电介质上方包括纳米点，并且在纳米点上包括保护膜。 在另一个存储单元中，电荷存储节点包括包含钌合金的纳米点。 存储器单元可以包括在保护膜或钌合金纳米点上的栅极间电介质和栅极间电介质上的控制栅极。 保护膜和钌合金可以被配置为在形成栅极间电介质期间保护至少一些纳米点不被蒸发。