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    AN APPARATUS AND METHOD FOR DICING AN IC SUBSTRATE
    1.
    发明申请
    AN APPARATUS AND METHOD FOR DICING AN IC SUBSTRATE 审中-公开
    一种用于定位IC基板的装置和方法

    公开(公告)号：WO2009035419A3

    公开(公告)日：2010-10-14

    申请号：PCT/SG2008000346

    申请日：2008-09-12

    Applicant: ROKKO VENTURES PTE LTD ,  YANG HAE CHOON ,  SHIN YUN SUK

    Inventor： YANG HAE CHOON ,  SHIN YUN SUK

    IPC: B28D5/00 ,  H01L21/00 ,  H01L21/677

    CPC classification number: B28D5/0082

    Abstract: An apparatus (5) for dicing an integrated circuit substrate having a loader (30) for loading the substrate to the apparatus, said substrate loaded in a first direction corresponding to a loading axis, an inlet rail (35) said inlet rail including a first block (75) movable along said inlet rail (35) to which is loaded the substrate from said loader, wherein said inlet rail is arranged to deliver the first block (75) and substrate towards a chuck table (60) in a second direction orthogonal to the loading axis.

    Abstract translation: 一种用于对集成电路基板进行切割的设备（5），所述集成电路基板具有用于将所述基板装载到所述装置的装载器（30），所述基板沿对应于加载轴线的第一方向装载，所述入口轨道（35）包括第一 沿着所述入口轨道（35）移动的块（75），从所述入口轨道（35）向所述入口轨道（35）移动，所述入口轨道布置成沿第二方向正交地将第一块（75）和衬底朝着卡盘台 到加载轴。

    PUNCH SINGULATION SYSTEM AND METHOD
    4.
    发明申请
    PUNCH SINGULATION SYSTEM AND METHOD 审中-公开
    PUNCH SINGULATION系统和方法

    公开(公告)号：WO2011037543A1

    公开(公告)日：2011-03-31

    申请号：PCT/SG2010/000360

    申请日：2010-09-24

    Applicant: ROKKO TECHNOLOGY PTE LTD. ,  YANG, Hae Choon ,  SHEN, Xue Fang ,  JANG, Deok Chun ,  LIM, Chong Chen, Gary ,  LIM, Siok Chun ,  SHIN, Yun Suk

    Inventor： YANG, Hae Choon ,  SHEN, Xue Fang ,  JANG, Deok Chun ,  LIM, Chong Chen, Gary ,  LIM, Siok Chun ,  SHIN, Yun Suk

    IPC: H01L21/78 ,  H01L21/677 ,  B21D28/00 ,  H01L21/68

    CPC classification number: H01L21/67092 ,  H01L21/67132 ,  Y10T83/647 ,  Y10T83/6572

    Abstract: A punching system for singulating IC units comprising: a punching assembly arranged to receive a substrate and singulate said substrate into the IC units; a rotary carrier rotatable from a first position to a second position said rotary carrier arranged to receive said units at the first position and carry said units to the second position through rotation; wherein said rotary carrier includes recesses for receiving at least a portion of the units. A punching assembly comprising a die block having recesses for receiving selectively replaceable inserts wherein said inserts correspond to a punch pattern specific to a predetermined IC package arrangement.

    Abstract translation: 一种用于分离IC单元的冲压系统，包括：冲压组件，布置成接收衬底并将所述衬底分离成IC单元; 旋转载体，可从第一位置旋转到第二位置，所述旋转载体布置成在第一位置处接收所述单元，并通过旋转将所述单元运送到第二位置; 其中所述旋转载体包括用于容纳所述单元的至少一部分的凹部。 一种冲压组件，其包括具有用于接收可选择性地替换的插入件的凹部的模具块，其中所述插入件对应于特定于预定IC封装布置的冲压模式。

    NET BLOCK ASSEMBLY
    5.
    发明申请
    NET BLOCK ASSEMBLY 审中-公开
    网块组装

    公开(公告)号：WO2008060244A2

    公开(公告)日：2008-05-22

    申请号：PCT/SG2007/000373

    申请日：2007-11-05

    Applicant: ROKKO SYSTEMS PTE LTD ,  LING, Nee Seng ,  ANG, Soo Loo ,  LIM, Chong Chen ,  BAEK, Seung Ho ,  JUNG, Jong Jae ,  SHIN, Yun Suk

    Inventor： LING, Nee Seng ,  ANG, Soo Loo ,  LIM, Chong Chen ,  BAEK, Seung Ho ,  JUNG, Jong Jae ,  SHIN, Yun Suk

    IPC: H01L21/00 ,  B28D5/00

    CPC classification number: B28D5/0088 ,  B28D5/0094 ,  H01L21/67092 ,  H01L21/67144 ,  H01L21/67271

    Abstract: The present invention relates to a net block assembly in a system for positioning singulated integrated circuits, having a net block surface partially covered by a two dimensional array of first and second elements, each first element having an aperture provided with vacuum adapted to receive an integrated circuit and each second element projecting from the surface said net block assembly including a plurality of rows of first and second element arranged in a chequer pattern, wherein the number of elements in the row is an odd number and a buffer row in the array having two first elements arranged adjacent to each other, wherein the number of elements in the buffer row is an odd number.

    Abstract translation: 本发明涉及一种用于定位单块集成电路的系统中的网块组件，其具有由第一和第二元件的二维阵列部分地覆盖的网状块表面，每个第一元件具有设置有适于接收集成 电路和每个第二元件从表面突出，所述网块组件包括以棋子图案布置的多行第一和第二元件，其中该行中的元件数量是奇数，并且阵列中的缓冲器行具有两个 彼此相邻布置的第一元件，其中缓冲行中的元素的数量是奇数。

    METHOD AND APPARATUS FOR IMPROVED SORTING OF DICED SUBSTRATES
    8.
    发明申请
    METHOD AND APPARATUS FOR IMPROVED SORTING OF DICED SUBSTRATES 审中-公开
    用于改进分层基板分选的方法和设备

    公开(公告)号：WO2011068478A1

    公开(公告)日：2011-06-09

    申请号：PCT/SG2010000447

    申请日：2010-11-30

    Applicant: ROKKO SYSTEMS PTE LTD ,  JUNG JONG JAE ,  SHIN YUN SUK ,  YANG HAE CHOON ,  JANG DEOK CHUN

    Inventor： JUNG JONG JAE ,  SHIN YUN SUK ,  YANG HAE CHOON ,  JANG DEOK CHUN

    IPC: H01L21/66 ,  B07C5/02 ,  B07C5/34 ,  H01L21/67

    CPC classification number: H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for inspecting and sorting a plurality of IC units comprising the steps of: delivering a frame containing said IC units to a unit picking station; conducting a first inspection of said units during the delivering step and recording the subsequent result; removing said units from the frame, and moving said units from the unit picking station to a flipping station; conducting a second inspection of said units during the moving step and recording the subsequent result; flipping said units to expose an opposed face said units; conducting a third inspection of said opposed face and recording the subsequent result, then; sorting said units into categories based on the recorded results from the first, second and third inspecting steps.

    Abstract translation: 一种用于检查和分类多个IC单元的方法，包括以下步骤：将包含所述IC单元的框架传送到单元拾取工位; 在递送步骤期间对所述单元进行第一次检查并记录后续结果; 从框架中取出所述单元，并将所述单元从单元拾取工位移动到翻转工位; 在移动步骤期间对所述单元进行第二次检查并记录后续结果; 翻转所述单元以暴露所述单元的相对面; 然后对所述相对面进行第三次检查并记录后续结果; 根据第一，第二和第三检查步骤的记录结果将所述单元分类成类别。

    NET BLOCK ASSEMBLY
    9.
    发明申请
    NET BLOCK ASSEMBLY 审中-公开
    网块组装

    公开(公告)号：WO2008060244A3

    公开(公告)日：2008-07-10

    申请号：PCT/SG2007000373

    申请日：2007-11-05

    Applicant: ROKKO SYSTEMS PTE LTD ,  LING NEE SENG ,  ANG SOO LOO ,  LIM CHONG CHEN ,  BAEK SEUNG HO ,  JUNG JONG JAE ,  SHIN YUN SUK

    Inventor： LING NEE SENG ,  ANG SOO LOO ,  LIM CHONG CHEN ,  BAEK SEUNG HO ,  JUNG JONG JAE ,  SHIN YUN SUK

    IPC: H01L21/00 ,  B28D5/00

    CPC classification number: B28D5/0088 ,  B28D5/0094 ,  H01L21/67092 ,  H01L21/67144 ,  H01L21/67271

    Abstract: The present invention relates to a net block assembly in a system for positioning singulated integrated circuits, having a net block surface partially covered by a two dimensional array of first (12) and second elements (14), each first element (12) having an aperture provided with vacuum adapted to receive an integrated circuit and each second element (14) projecting from the surface said net block assembly including a plurality of rows of first (12) and second element (14) arranged in a chequer pattern, wherein the number of elements in the row is an odd number and a buffer row (16) in the array having two first elements (12) arranged adjacent to each other, wherein the number of elements in the buffer row (16) is an odd number.

    Abstract translation: 本发明涉及一种用于定位单片集成电路的系统中的网块组件，其具有由第一（12）和第二元件（14）的二维阵列部分地覆盖的网块表面，每个第一元件（12）具有 具有适于接纳集成电路的真空的孔，以及从所述表面突出的每个第二元件（14），所述网块组件包括以棋盘图案布置的多行第一（12）和第二元件（14），其中所述数 该行中的元件是具有彼此相邻布置的两个第一元件（12）的阵列中的奇数和缓冲器行（16），其中缓冲器行（16）中的元件数量是奇数。

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