公开(公告)号：WO2016169818A1

公开(公告)日：2016-10-27

申请号：PCT/EP2016/058057

申请日：2016-04-13

Applicant: ABB TECHNOLOGY AG

Inventor： MATTHIAS, Sven ,  PAPADOPOULOS, Charalampos ,  CORVASCE, Chiara ,  KOPTA, Arnost

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/06 ,  H01L21/304

CPC classification number: H01L21/32131 ,  H01L21/304 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/402 ,  H01L29/41708 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/7397

Abstract: A method for manufacturing a power semiconductor device is provided. The method comprises the following steps: providing a wafer (41) of a first conductivity type, the wafer (41) having a first main side (42) and a second main side (43) opposite to the first main side (42), and the wafer (41) including an active cell area (44), which extends from the first main side (42) to the second main side (43), in a central part of the wafer (41) and a termination area (45) surrounding the active cell area (44) in an orthogonal projection onto a plane parallel to the first main side (42); forming a metallization layer (46; 86) on the first main side (42) to electrically contact the wafer (41) in the active cell area (44), wherein the surface of the metallization layer (46; 86), which faces away from the wafer (41), defines a first plane (B) parallel to the first main side (42); forming an isolation layer (417) on the first main side (42) in the termination area (45), wherein the surface of the isolation layer (417) facing away from the wafer (41) defines a second plane (A) parallel to the first main side (42); after the step of forming the metallization layer (46; 86) and after the step of forming the isolation layer (417), mounting the wafer (41) with its first main side to a flat surface of a chuck (421); and thereafter thinning the wafer (41) from its second main side (43) by grinding while pressing the second main side of the wafer (41) onto a grinding wheel (422) by applying a pressure between the chuck (421) and the grinding wheel (422), wherein the first plane (B) is further away from the wafer (41) than a third plane, which is parallel to the second plane (A) and arranged at a distance of 1 μιη from the second plane (A) in a direction towards the wafer (41).

Abstract translation: 提供一种制造功率半导体器件的方法。 该方法包括以下步骤：提供第一导电类型的晶片（41），晶片（41）具有与第一主侧（42）相对的第一主侧（42）和第二主侧（43） 并且所述晶片（41）包括在所述晶片（41）的中心部分中从所述第一主侧（42）延伸到所述第二主侧（43）的活性电池区域（44）和端接区域（45） ）以平行于所述第一主侧（42）的平面的正交投影方式围绕所述有源单元区域（44）; 在所述第一主侧（42）上形成金属化层（46; 86）以电接触所述活性电池区域（44）中的所述晶片（41），其中所述金属化层（46; 86） 从所述晶片（41）限定平行于所述第一主侧（42）的第一平面（B）; 在所述终止区域（45）中的所述第一主侧（42）上形成隔离层（417），其中所述隔离层（417）的远离所述晶片（41）的表面限定平行于 第一主面（42）; 在形成金属化层（46; 86）的步骤之后，并且在形成隔离层（417）的步骤之后，将其第一主侧的晶片（41）安装到卡盘（421）的平坦表面; 然后通过研磨将晶片（41）从其第二主侧（43）减薄，同时通过在卡盘（421）和研磨之间施加压力将晶片（41）的第二主侧压入砂轮（422） 轮（422），其中所述第一平面（B）比与所述第二平面（A）平行且与所述第二平面（A）成1微米的距离的第三平面离所述晶片（41）更远 ）朝向晶片（41）的方向。

公开(公告)号：WO2016071064A1

公开(公告)日：2016-05-12

申请号：PCT/EP2015/073136

申请日：2015-10-07

Applicant: ABB TECHNOLOGY AG

Inventor： JANISCH, Wolfgang ,  MATTHIAS, Sven ,  DE VRIES, Atze

IPC: H01L21/762

CPC classification number: H01L21/76251

Abstract: It is the object of the invention to provide a semiconductor device manufacturing method including a step of bonding a first wafer (101) to a second wafer (115), wherein local damage of the first wafer (101) or the second wafer (115), and in particular splitting- off of parts of one wafer from the other wafer, during process steps subsequent to the bonding step can be avoided in an efficient and cost-efficient manner. This object is solved by a semiconductor device manufacturing method including, subsequent to a bonding step between a first wafer (101) and a second wafer (115), a step of forming a sealing layer (200) onto the surface of the wafer stack formed in the bonding step, wherein the sealing layer (200) seals up a gap between the first wafer (101) and the second wafer (115) to prevent penetration of gas or fluid into the gap during subsequent process steps.

Abstract translation: 本发明的目的是提供一种半导体器件制造方法，包括将第一晶片（101）接合到第二晶片（115）的步骤，其中第一晶片（101）或第二晶片（115）的局部损坏 并且特别是在一个晶片的部分从另一个晶片分离之后，在接合步骤之后的工艺步骤期间可以以有效和成本有效的方式避免。 该目的通过一种半导体器件制造方法来解决，该方法包括：在第一晶片（101）和第二晶片（115）之间的接合步骤之后，在形成的晶片堆叠的表面上形成密封层（200）的步骤 在所述接合步骤中，所述密封层（200）密封所述第一晶片（101）和所述第二晶片（115）之间的间隙，以防止在随后的工艺步骤期间气体或流体渗透到所述间隙中。

公开(公告)号：WO2016041852A1

公开(公告)日：2016-03-24

申请号：PCT/EP2015/070793

申请日：2015-09-11

Applicant: ABB TECHNOLOGY AG

Inventor： JANISCH, Wolfgang ,  DE VRIES, Atze ,  MATTHIAS, Sven

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/225 ,  H01L29/739 ,  H01L29/744 ,  H01L29/08 ,  H01L21/20

CPC classification number: H01L21/225 ,  H01L21/2007 ,  H01L21/2253 ,  H01L21/2256 ,  H01L21/283 ,  H01L21/673 ,  H01L21/76256 ,  H01L29/0834 ,  H01L29/0873 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/7395 ,  H01L29/744

Abstract: A method for manufacturing a vertical power semiconductor device is provided, wherein a first impurity is provided at the first main side (103) of a semiconductor wafer (101). A first oxide layer (112) is formed on the first main side (103) of the wafer (101), wherein the first oxide layer (112) is partially doped with a second impurity in such way that any first portion of the first oxide layer (112) which is doped with the second impurity is spaced away from the semiconductor wafer by a second portion of the first oxide layer (112) which is not doped with the second impurity and which is disposed between the first portion of the first oxide layer (112) and the first main side (103) of the semiconductor wafer (101). Thereafter a carrier wafer (115) is bonded to the first oxide layer (112). During front-end-of-line processing on the second main side (102) of the semiconductor wafer (101), the second impurity is diffused from the first oxide layer (112) into the semiconductor wafer (101) from its first main side (103) by heat generated during the front-end-of-line processing.

Abstract translation: 提供一种用于制造垂直功率半导体器件的方法，其中在半导体晶片（101）的第一主侧（103）处设置第一杂质。 第一氧化物层（112）形成在晶片（101）的第一主侧（103）上，其中第一氧化物层（112）部分地掺杂有第二杂质，使得第一氧化物 掺杂有第二杂质的层（112）通过未掺杂第二杂质的第一氧化物层（112）的第二部分与半导体晶片隔开，并且设置在第一氧化物的第一部分之间 层（112）和半导体晶片（101）的第一主侧（103）。 此后，载体晶片（115）与第一氧化物层（112）结合。 在半导体晶片（101）的第二主面（102）的前端处理中，第二杂质从第一主面从第一氧化物层（112）扩散到半导体晶片（101） （103）通过在前端处理期间产生的热量。