公开(公告)号：WO2021043635A1

公开(公告)日：2021-03-11

申请号：PCT/EP2020/073740

申请日：2020-08-25

Applicant: AMS AG

Inventor： KRAFT, Jochen ,  STERING, Bernhard ,  STEELE, Colin ,  SEURIN, Jean Francois

IPC: G02B6/42

Abstract: A bonded structure (1) comprises a substrate component (20) having a plurality of first pads (21) arranged on or within a surface (22) of the substrate component (20), and an integrated circuit component (10) having a plurality of second pads (11) arranged on or within a surface (12) of the integrated circuit component (10). The bonded structure (1) further comprises a plurality of connection elements (31) physically connecting the first pads (21) to the second pads (11). The surface (12) of the integrated circuit component (10) is tilted obliquely to the surface (22) of the substrate component (22) at a tilt angle (α) that results from nominal variations of surface sizes of the first and second pads (21, 11).

公开(公告)号：WO2019193067A1

公开(公告)日：2019-10-10

申请号：PCT/EP2019/058430

申请日：2019-04-03

Applicant: AMS AG

Inventor： KRAFT, Jochen ,  PARTEDER, Georg ,  JESSENIG, Stefan ,  SCHRANK, Franz ,  SIEGERT, Jörg

IPC: H01L21/768 ,  H01L23/48

Abstract: A substrate (1) is provided with a dielectric (2), a metal layer (3) embedded in the dielectric, and a metallic layer (4) arranged on the metal layer between the substrate and the metal layer. A via hole (9) is formed in the substrate and in a region of the dielectric that is between the substrate and the metal layer. An insulation layer (11) is applied in the via hole and removed from above a contact area (10) of the metal layer, and the metallic layer is completely removed from the contact area (10). A metallization (12) is applied in the via hole on the contact area.

公开(公告)号：WO2015082203A1

公开(公告)日：2015-06-11

申请号：PCT/EP2014/074786

申请日：2014-11-17

Applicant: AMS AG

Inventor： KRAFT, Jochen ,  SIEGERT, Jörg ,  STÜCKLER, Ewald

IPC: G02B6/42 ,  G02B6/12 ,  H05K1/02

CPC classification number: G02B6/122 ,  G02B6/12004 ,  G02B6/132 ,  G02B6/136 ,  G02B6/4214 ,  G02B6/43 ,  G02B2006/12104

Abstract: The semiconductor device comprises a substrate (1) of semiconductor material, a dielectric layer (2) above the substrate, a waveguide (3) arranged in the dielectric layer, and a mirror region (4) arranged on a surface of a mirror support (5) integrated on the substrate, the mirror support being a high-density plasma deposited oxide. A mirror is thus formed facing the waveguide. The surface of the mirror support and hence the mirror are inclined with respect to the waveguide.

Abstract translation: 半导体器件包括半导体材料的衬底（1），衬底上的电介质层（2），布置在电介质层中的波导（3）和布置在反射镜支撑体的表面上的反射镜区域（4） 5）集成在基板上，镜支架是高密度等离子体沉积氧化物。 因此形成面向波导的反射镜。 反射镜支撑体的表面，因此反射镜相对于波导管倾斜。

公开(公告)号：WO2015055480A1

公开(公告)日：2015-04-23

申请号：PCT/EP2014/071560

申请日：2014-10-08

Applicant: AMS AG

Inventor： KRAFT, Jochen ,  ROHRACHER, Karl ,  TEVA, Jordi

IPC: G02B6/42 ,  G02B6/43 ,  H05K1/02 ,  H05K3/46 ,  H01L23/48

CPC classification number: G02B6/4283 ,  G02B6/12002 ,  G02B6/13 ,  G02B6/4274 ,  G02B6/428 ,  G02B6/43 ,  G02B2006/121 ,  G02B2006/12107 ,  G02B2006/12121 ,  G02B2006/12123 ,  G02B2006/12147 ,  H01L23/481 ,  H01L23/522 ,  H01L31/16 ,  H01L2224/16225 ,  H05K1/0274 ,  H05K1/115 ,  H05K1/116 ,  H05K1/181 ,  H05K3/429 ,  H05K3/4605 ,  H05K2201/0939 ,  H05K2201/09518 ,  H05K2201/09581 ,  H05K2201/10174

Abstract: The method comprises providing a semiconductor substrate (1), which has a main surface (12) and an opposite further main surface (13), arranging a contact pad (19) above the further main surface, forming a through-substrate via (4) from the main surface to the further main surface at a distance from the contact pad and, by the same method step together with the through-substrate via, forming a further through- substrate via (14) above the contact pad, arranging a hollow metal via layer (5) in the through-substrate via and, by the same method step together with the metal via layer, arranging a further metal via layer (15) in the further through- substrate via, the further metal via layer contacting the contact pad, and removing a bottom portion of the metal via layer to form an optical via laterally surrounded by the metal via layer.

Abstract translation: 该方法包括提供具有主表面（12）和相对的另外的主表面（13）的半导体衬底（1），在另一主表面上方布置接触焊盘（19），通过（4） ）从主表面到另一个主表面，距离接触焊盘一定距离，并且通过与通孔基板通孔相同的方法步骤，在接触焊盘上方通过（14）形成另外的通孔基板， 金属通孔层（5），并且通过与金属通孔层一起的相同方法步骤，在另外的通孔中经由另外的金属通孔层（15），将另外的金属通孔层 接触垫，并且去除金属通孔层的底部以形成由金属通孔层横向包围的光学通孔。

公开(公告)号：WO2019211041A1

公开(公告)日：2019-11-07

申请号：PCT/EP2019/056964

申请日：2019-03-20

Applicant: AMS AG

Inventor： KRAFT, Jochen ,  PARTEDER, Georg ,  SINGULANI, Anderson ,  COPPETA, Raffaele ,  SCHRANK, Franz

IPC: H01L23/48

Abstract: A semiconductor device (10) comprises a semiconductor body (11), an electrically conductive via (12) which extends through at least a part of the semiconductor body (11), and where the via (12) has a top side (13) and a bottom side (14) that faces away from the top side (13), an electrically conductive etch-stop layer (15) arranged at the bottom side (14) of the via (12) in a plane which is parallel to a lateral direction (x), where the lateral direction (x) is perpendicular to a vertical direction (z) given by the main axis of extension of the via (12), and at least one electrically conductive contact layer (16) at the bottom side (14) of the via (12) in a plane which is parallel to the lateral direction (x). The etch-stop layer (16) is arranged between the electrically conductive via (12) and the contact layer (16) in the vertical direction (z), the lateral extent in the lateral direction (x) of the etch-stop layer (15) amounts to at least 2.5 times the lateral extent of the via (12) in the lateral direction (x), and the lateral extent of the contact layer (16) is smaller than the lateral extent of the via (12) or the lateral extent of the contact layer (16) amounts to at least 2.5 times the lateral extent of the via (12).

公开(公告)号：WO2019057436A1

公开(公告)日：2019-03-28

申请号：PCT/EP2018/072767

申请日：2018-08-23

Applicant: AMS AG

Inventor： PARTEDER, Georg ,  KRAFT, Jochen ,  COPPETA, Raffaele

IPC: H01L21/768 ,  H01L23/48

Abstract: A method for manufacturing a semiconductor device (10) is provided. The method comprises the steps of providing a semiconductor body (11), forming a trench (12) in the semiconductor body (11) in a vertical direction (z) which is perpendicular to the main plane of extension of the semiconductor body (11), and coating inner walls (13) of the trench (12) with an isolation layer (14). The method further comprises the steps of coating the isolation layer (14) at the inner walls (13) with a metallization layer (15), coating a top side (16) of the semiconductor body (11), at which the trench (12) is formed, at least partially with an electrically conductive contact layer (17), where the contact layer (17) is electrically connected with the metallization layer (15), coating the top side (16) of the semiconductor body (11) at least partially and the trench (12) with a capping layer (24), and forming a contact pad (18) at the top side (16) of the semiconductor body (11) by removing the contact layer (17) and the capping layer (24) at least partially. Furthermore, a semiconductor device (10) is provided.

公开(公告)号：WO2014108442A1

公开(公告)日：2014-07-17

申请号：PCT/EP2014/050233

申请日：2014-01-08

Applicant: AMS AG

Inventor： SIEGERT, Jörg ,  SCHREMS, Martin ,  KRAFT, Jochen ,  SCHRANK, Franz

IPC: H01L21/683

CPC classification number: H01L21/6836 ,  H01L21/6835 ,  H01L21/76898 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  Y10T156/10

Abstract: A device wafer (1) having a main surface (10) including an edge region (11) and a carrier (2) having a further main surface (20) including an annular surface region (21) corresponding to the edge region of the device wafer are provided. An adhesive (3) is applied in the edge region and/or in the annular surface region, but not on the remaining areas of the main surfaces. The device wafer is fastened to the carrier by the adhesive. The main surface and the further main surface are brought into contact with one another when the device wafer is fastened to the carrier, while the main surface and the further main surface are fastened to one another only in the edge region. The device wafer is removed from the carrier after further process steps, which may include the formation of through-wafer vias in the device wafer.

Abstract translation: 一种器件晶片（1），具有包括边缘区域（11）的主表面（10）和具有另外的主表面（20）的载体（2），所述主表面包括对应于所述装置的边缘区域的环形表面区域 提供晶片。 粘合剂（3）施加在边缘区域和/或环形表面区域中，而不是在主表面的剩余区域上。 器件晶片通过粘合剂固定到载体上。 当装置晶片被固定到载体上时，主表面和另一个主表面彼此接触，而主表面和另外的主表面仅在边缘区域彼此紧固。 在进一步的工艺步骤之后，器件晶片从载体上移除，其可以包括在器件晶片中形成贯通晶片通孔。

公开(公告)号：WO2021043661A1

公开(公告)日：2021-03-11

申请号：PCT/EP2020/073957

申请日：2020-08-27

Applicant: AMS AG

Inventor： PARTEDER, Georg ,  KRAFT, Jochen ,  JESSENIG, Stefan

IPC: H01L23/48

Abstract: An open through-substrate via (1), TSV, comprises an insulation layer (20) disposed adjacent to at least a portion of side walls (15) of a trench (14) and to a surface (13) of a substrate body (10). The TSV further comprises a metallization layer (30) disposed adjacent to at least a portion of the insulation layer (20) and to at least a portion of a bottom wall (16) of said trench (14), a redistribution layer (40) disposed adjacent to at least a portion of the metallization layer (30) and a portion of the insulation layer (20) disposed adjacent to the surface (13), and a capping layer (50) disposed adjacent to at least a portion of the metallization layer (30) and to at least a portion of the redistribution layer (40). The insulation layer (20) and/or the capping layer (50) comprise sublayers (21, 22, 51, 52) that are distinct from each other in terms of material properties. A first of the sublayers (21, 51) is disposed adjacent to at least a portion of the side walls (15) and to at least a portion of the surface (13) and a second of the sublayers (22, 52) is disposed adjacent to at least a portion of the surface (13).

公开(公告)号：WO2019115698A1

公开(公告)日：2019-06-20

申请号：PCT/EP2018/084772

申请日：2018-12-13

Applicant: AMS AG ,  TECHNISCHE UNIVERSITÄT GRAZ

Inventor： KRAFT, Jochen ,  RÖHRER, Georg ,  CASTANO, Fernando ,  SINGULANI, Anderson ,  MAIERHOFER, Paul

IPC: G01N15/06 ,  G01N21/53 ,  G01N15/00

CPC classification number: G01N15/06 ,  G01N21/534 ,  G01N2015/0026 ,  G01N2015/03 ,  G01N2015/0693

Abstract: The particle sensor device comprises a substrate (1), a photodetector (3), a dielectric (4) on or above the substrate (1), a source of electromagnetic radiation (5), and a through-substrate via (6) in the substrate (1). The through- substrate via is exposed to the environment, in particular to ambient air. A waveguide (7) is arranged in or above the dielectric so that the electromagnetic radiation emitted by the source of electromagnetic radiation is coupled into a portion (7.1) of the waveguide. A further portion (7.2) of the waveguide is opposite the photodetector, so that said portions of the waveguide are on different sides of the through-substrate via, and the waveguide traverses the through-substrate via.

公开(公告)号：WO2018149883A1

公开(公告)日：2018-08-23

申请号：PCT/EP2018/053694

申请日：2018-02-14

Applicant: AMS AG

Inventor： KRAFT, Jochen ,  PARTEDER, Georg ,  SINGULANI, Anderson ,  COPPETA, Raffaele ,  SCHRANK, Franz

IPC: H01L23/48

Abstract: A semiconductor device(10) comprises a semiconductor body (11) and an electrically conductive via (12) which extends through at least a part of the semiconductor body (11), where the via (12) has a lateral size which is given in a first lateral direction (x) that is perpendicular to a vertical direction (z) given by the main axis of extension of the via (12) and where the via (12) has a top side (13) and a bottom side (14) that faces away from the top side (13). The semiconductor device (10) further comprises an electrically conductive etch-stop layer (15) arranged at the bottom side (14) of the via (12) in a plane which is parallel to the first lateral direction (x), and at least one electrically conductive contact layer (16) at the bottom side (14) of the via (12) in a plane which is parallel to the first lateral direction (x). The lateral extent in the first lateral direction (x) of the etch-stop layer (15) is larger than the lateral size of the via (12) and the lateral extent in the first lateral direction (x) of the contact layer (16) is smaller than the lateral size of the via (12). Furthermore, the etch-stop layer (15) is arranged between the electrically conductive via (12) and the contact layer (16) in the vertical direction (z).