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    METHOD FOR EXTRACTING THE DISTRIBUTION OF CHARGE STORED IN A SEMICONDUCTOR DEVICE
    6.
    发明申请
    METHOD FOR EXTRACTING THE DISTRIBUTION OF CHARGE STORED IN A SEMICONDUCTOR DEVICE 审中-公开
    提取存储在半导体器件中的电荷分布的方法

    公开(公告)号：WO2006128922A1

    公开(公告)日：2006-12-07

    申请号：PCT/EP2006/062944

    申请日：2006-06-06

    申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW ,  FURNÉMONT, Arnaud

    发明人： FURNÉMONT, Arnaud

    IPC分类号： G11C16/26 ,  G11C11/56

    CPC分类号： G11C16/0475 ,  G11C16/26 ,  G11C16/3495

    摘要： The invention relates to a method for determining a set of programming conditions for a given type of charge-trapping non-volatile memory device, comprising the steps of: (a) selecting different sets of programming parameters to be applied to the corresponding number of non-volatile memory devices of said type, (b) programming said number of non-volatile memory devices by means of the sets of programming parameters, (c) determining an actual spatial charge distribution of the charge trapping layer of each of the programmed devices, (d) determining the influence of at least one of the programming parameters on the spatial charge distribution, (e) determining an optimised value for at least one of the programming parameters, (f) entering each optimised value in said sets of programming parameters and repeating steps b) to e) at least once.

    摘要翻译： 本发明涉及一种用于确定给定类型的电荷捕获非易失性存储器件的一组编程条件的方法，包括以下步骤：（a）选择不同的编程参数集合以应用于相应数量的非易失性存储器件， 所述类型的非挥发性存储器件，（b）通过所述编程参数组对所述数量的非易失性存储器件进行编程，（c）确定每个编程器件的电荷俘获层的实际空间电荷分布， （d）确定所述编程参数中的至少一个对所述空间电荷分布的影响，（e）确定所述编程参数中的至少一个的优化值，（f）在所述编程参数组中输入每个优化值，以及 重复步骤b）至e）至少一次。

    PHOTOVOLTAIC CELL WITH THICK SILICON OXIDE AND SILICON NITRIDE PASSIVATION FABRICATION
    7.
    发明申请
    PHOTOVOLTAIC CELL WITH THICK SILICON OXIDE AND SILICON NITRIDE PASSIVATION FABRICATION 审中-公开
    具有硅氧化硅和硅氮化物钝化膜的光电池

    公开(公告)号：WO2006097303A1

    公开(公告)日：2006-09-21

    申请号：PCT/EP2006/002409

    申请日：2006-03-16

    申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW ,  AGOSTINELLI, Guido ,  BEAUCARNE, Guy ,  CHOULAT, Patrick

    发明人： AGOSTINELLI, Guido ,  BEAUCARNE, Guy ,  CHOULAT, Patrick

    IPC分类号： H01L31/18 ,  H01L31/0216 ,  H01L31/0224 ,  H01L31/02

    CPC分类号： H01L31/02167 ,  H01L31/022425 ,  H01L31/18 ,  H01L31/1868 ,  Y02E10/50 ,  Y02P70/521

    摘要： A method for the production of a photovoltaic device, for instance solar cell, is disclosed, comprising the steps of providing a substrate having a front main surface and a rear surface; depositing a dielectric layer on the rear surface, wherein the dielectric layer has a thickness larger than 100 nm; depositing a passivation layer comprising hydrogenated SiN on top of the dielectric layer and forming back contacts through the dielectric layer and the passivation layer. A method for the production of a photovoltaic device, for instance solar cell, is also disclosed, comprising the steps of providing a substrate having a front main surface and a rear surface; depositing a dielectric layer stack on the rear surface, wherein the dielectric layer stack comprises a sub-stack of dielectric layers, the sub-stack having a thickness larger than 100 nm, the dielectric layer stack having a thickness larger than 200 nm; and forming back contacts through the dielectric layer stack. Corresponding photovoltaic devices, for instance solar cell devices, are also disclosed.

    摘要翻译： 公开了一种用于生产光伏器件（例如太阳能电池）的方法，包括以下步骤：提供具有前主表面和后表面的衬底; 在后表面上沉积介电层，其中介电层的厚度大于100nm; 在电介质层的顶部上沉积包括氢化SiN的钝化层，并通过介电层和钝化层形成后接触。 还公开了用于制造光伏器件（例如太阳能电池）的方法，包括以下步骤：提供具有前主表面和后表面的衬底; 在后表面上沉积介电层堆叠，其中所述电介质层堆叠包括电介质层的子堆叠，所述子堆叠具有大于100nm的厚度，所述电介质层堆叠具有大于200nm的厚度; 并通过介电层堆叠形成后接触。 还公开了相应的光伏器件，例如太阳能电池器件。

    LITHOGRAPHIC PROJECTION DEVICE, METHOD AND SUBSTRATE FOR MANUFACTURING ELECTRONIC DEVICES, AND OBTAINED ELECTRONIC DEVICE
    8.
    发明申请
    LITHOGRAPHIC PROJECTION DEVICE, METHOD AND SUBSTRATE FOR MANUFACTURING ELECTRONIC DEVICES, AND OBTAINED ELECTRONIC DEVICE 审中-公开
    光刻投影装置，用于制造电子装置的方法和基板以及所获得的电子装置

    公开(公告)号：WO2005064407A2

    公开(公告)日：2005-07-14

    申请号：PCT/IB2004/052690

    申请日：2004-12-07

    申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW ,  DIRKSEN, Peter

    发明人： DIRKSEN, Peter

    IPC分类号： G03F7/20

    CPC分类号： G03F7/70308 ,  G03F7/70633

    摘要： The invention proposes a lithographic projection device such as a wafer stepper for forming a pattern on a substrate or wafer, comprising a(n) (actinic) radiation or light source (2), illumination optics (4) for directing light issuing from said light source onto a mask (6) and projection optics (8) for directing diffracted radiation or light from said mask to the substrate/wafer to be imaged, wherein an optical filter (9) is provided downstream of said projection optics and an imageable substrate (7) having an optical filter (9) on the side to be imaged.

    摘要翻译： 本发明提出了一种光刻投影装置，例如用于在衬底或晶片上形成图案的光刻投影装置，包括（n）（光化）辐射或光源（2），照明光学器件（4），用于引导从所述光 来源于掩模（6）和投影光学器件（8），用于将衍射的辐射或来自所述掩模的光引导到待成像的衬底/晶片，其中在所述投影光学器件的下游提供滤光器（9）和可成像衬底（ 7）在要成像的一侧具有滤光器（9）。

    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED BY USING SUCH A METHOD
    9.
    发明申请
    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED BY USING SUCH A METHOD 审中-公开
    制造使用这种方法获得的半导体器件和半导体器件的方法

    公开(公告)号：WO2004070831A1

    公开(公告)日：2004-08-19

    申请号：PCT/IB2004/050026

    申请日：2004-01-15

    申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW, ,  FURUKAWA, Yukiko

    发明人： FURUKAWA, Yukiko

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76808 ,  H01L2221/1031

    摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a semiconductor body (1) and a substrate (2) comprising at least one semiconductor element (3) and provided with at least one connection region (4) and an overlying stripe-shaped connection conductor (5) which is connected to the connection region (4), which connection conductor and connection region are both recessed in a dielectric material, where subsequently a first dielectric layer (6), a hard mask layer (7), and a second dielectric layer (8) are deposited on the semiconductor body (1), where at the location of the connection region (4) to be formed, a via (44) is formed in the first dielectric layer (6) by means of plasma etching using a plasma containing a compound of carbon and fluor, and in the presence of a patterned fotoresist layer deposited on top of the structure and at the location of the connection conductor (6) to be formed, a trench (55) is formed in the second dielectric layer (8) by means of plasma etching, which via (44) and trench (55) are filled with an electrically conducting material in order to form, respectively, the connection region (4) and the connection conductor (5), and where before the trench (55) is formed, the already formed via (44) is filled with an organic material (20). According to the invention, the material of the first dielectric layer (6) and the etch conditions during formation of the via (44) in the first dielectric layer (6) by plasma etching are chosen such that during etching the via (44), said via (44) is at the same time substantially completely filled with the organic material (20), which organic material (20) is formed from organic material already present within the structure and within the plasma. Relevant conditions - apart from the presence of the resist layer during etching and the use therein of a compound of carbon and fluor - relate to the choice of the material of the first (and second) dielectric layer(s) 6,8 and the power during etching of these layers (6,8).

    摘要翻译： 本发明涉及一种制造具有半导体本体（1）的半导体器件（10）和包括至少一个半导体元件（3）并具有至少一个连接区域（4）和上覆 连接到连接区域（4）的条形连接导体（5），该连接导体和连接区域均凹入介电材料中，随后第一介电层（6），硬掩模层（7） ，并且在所述半导体主体（1）上沉积第二电介质层（8），其中在要形成的连接区域（4）的位置处，在第一介电层（6）中通过（44）形成通孔（44），通孔 使用含有碳和氟化合物的等离子体进行等离子体蚀刻的方法，并且在沉积在结构的顶部和待形成的连接导体（6）的位置处的图案化的光刻胶层存在下，形成沟槽（55） 在第二电介质层（8）中形成 等离子体蚀刻装置，其通过（44）和沟槽（55）填充有导电材料，以分别形成连接区域（4）和连接导体（5），并且在沟槽（55）之前 ），已经形成的通孔（44）填充有机材料（20）。 根据本发明，选择第一介电层（6）的材料和通过等离子体蚀刻在第一介电层（6）中形成通孔（44）期间的蚀刻条件，使得在蚀刻通孔（44）期间， 所述通孔（44）同时基本上完全填充有机材料（20），该有机材料（20）由已经存在于结构内部和等离子体内的有机材料形成。 相关条件 - 除了蚀刻期间抗蚀剂层的存在以及碳和氟化合物中的使用 - 涉及第一（和第二）电介质层6,8的材料的选择和功率 在蚀刻这些层（6,8）期间。

    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD
    10.
    发明申请
    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD 审中-公开
    制造半导体器件的方法和采用这种方法获得的半导体器件

    公开(公告)号：WO2004057659A1

    公开(公告)日：2004-07-08

    申请号：PCT/IB2003/006009

    申请日：2003-12-15

    申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW ,  VENEZIA, Vincent, C. ,  DACHS, Charles, J., J. ,  HOOKER, Jacob, C. ,  VAN DAL, Marcus, J., H.

    发明人： VENEZIA, Vincent, C. ,  DACHS, Charles, J., J. ,  HOOKER, Jacob, C. ,  VAN DAL, Marcus, J., H.

    IPC分类号： H01L21/28

    CPC分类号： H01L29/41783 ,  H01L21/26586 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/1045 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  Y10T307/74

    摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a field effect transistor, in which method a semiconductor body (1) of a semiconductor material is provided, at a surface thereof, with a source region (2) and a drain region (3) and with a gate region (4) between the source region (2) and the drain region (3), which gate region comprises a semiconductor region (4A) of a further semiconductor material that is separated from the surface of the semiconductor body (1) by a gate dielectric (5), and with spacers (6) adjacent to the gate region (4), for forming the source and drain regions (2,3), in which method the source region (2) and the drain region (3) are provided with a metal layer (7) which is used to form a compound (8) of the metal and the semiconductor material, and the gate region (4) is provided with a metal layer (7) which is used to form a compound (8) of the metal and the further semiconductor material. The known method in which different metal layers are used to silicidate source and drain regions and gate regions (2,3,4) has several drawbacks. A method according to the invention is characterized in that before the spacers (6) are formed, a sacrificial region (4B) of a material that may be selectively etched with respect to the semiconductor region (4A) is deposited on top of the semiconductor region (4A), and after the spacers (6) have been formed, the sacrificial layer (4B) is removed by etching, and after removal of the sacrificial layer (4B), a single metal layer (7) is deposited contacting the source, drain and gate regions (2,3,4). This method is on the one hand very simple as it requires only a single metal layer and few, straight-forward steps and it is compatible with existing (silicon) technology, and on the other hand it results in a (MOS)FET which does not suffer from a depletion layer effect in the fully silicided gate (4).

    摘要翻译： 本发明涉及一种制造具有场效应晶体管的半导体器件（10）的方法，该场效应晶体管在其表面上提供半导体材料的半导体本体（1），源极区（2）和 漏极区域（3）和源极区域（2）和漏极区域（3）之间的栅极区域（4），该栅极区域包括从其表面分离的另一半导体材料的半导体区域（4A） 半导体本体（1）通过栅极电介质（5）和与栅极区域（4）相邻的间隔物（6）形成源极和漏极区域（2,3），其中源区域（2） ）和漏区（3）设置有用于形成金属和半导体材料的化合物（8）的金属层（7），并且栅极区域（4）设置有金属层（7） ），其用于形成金属的化合物（8）和另外的半导体材料。 使用不同的金属层来硅化源极和漏极区域和栅极区域（2,3,4）的已知方法具有若干缺点。 根据本发明的方法的特征在于，在形成间隔物（6）之前，可以相对于半导体区域（4A）选择性地蚀刻的材料的牺牲区域（4B）沉积在半导体区域 （4A），并且在形成间隔物（6）之后，通过蚀刻去除牺牲层（4B），并且在去除牺牲层（4B）之后，沉积与源极接触的单个金属层（7） 漏极和栅极区域（2,3,4）。 这种方法一方面非常简单，因为它只需要单一的金属层和少量的直接步骤，并且它与现有的（硅）技术相兼容，另一方面它产生一个（MOS）FET 不会在完全硅化的栅极（4）中遭受耗尽层效应。