公开(公告)号：WO2017111838A1

公开(公告)日：2017-06-29

申请号：PCT/US2015/000396

申请日：2015-12-26

Applicant: INTEL CORPORATION

Inventor： LAMBERT, William, J. ,  ROY, Mihir, K. ,  MANUSHAROW, Mathew, J.

IPC: H01L23/48

CPC classification number: H05K1/185 ,  H05K3/0047 ,  H05K3/3436 ,  H05K2201/10454 ,  H05K2201/10651

Abstract: Embodiments are generally directed to vertically embedded passive components. An embodiment of a device includes a semiconductor die; and a package coupled with the semiconductor die. The package includes one or more passive components connected with the semiconductor die, the one or more passive components being embedded vertically in the package substrate, each of the passive components including a first terminal and a second terminal. A first passive component is embedded in a through hole drilled in the package, the first terminal of the first passive component being connected to the semiconductor die by a via through an upper buildup layer on the package.

Abstract translation: 实施例通常针对垂直嵌入的无源组件。 器件的实施例包括半导体管芯; 以及与半导体管芯耦合的封装。 封装包括与半导体管芯连接的一个或多个无源组件，所述一个或多个无源组件垂直嵌入封装基板中，每个无源组件包括第一端子和第二端子。 第一无源部件嵌入在封装中钻出的通孔中，第一无源部件的第一端子通过穿过封装上的上堆积层的通孔连接至半导体管芯。

公开(公告)号：WO2011059569A1

公开(公告)日：2011-05-19

申请号：PCT/US2010/049521

申请日：2010-09-20

Applicant: INTEL CORPORATION ,  GUZEK, John, S. ,  ROY, Mihir, K. ,  ROBERTS, Brent, M.

Inventor： ROY, Mihir, K. ,  ROBERTS, Brent, M.

IPC: H01L23/485 ,  H01L23/50 ,  H01L23/12 ,  H01L23/14

CPC classification number: H05K1/165 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/0254 ,  H05K1/0262 ,  H05K1/116 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A microelectronic device comprises a first substrate (110) having a first electrically conductive path (111) therein and a second substrate (120) above the first substrate and having a second electrically conductive path (121) therein, wherein the first electrically conductive path and the second electrically conductive path are electrically connected to each other and form a portion of a current loop (131) of an inductor (130).

Abstract translation: 微电子器件包括其中具有第一导电路径（111）的第一衬底（110）和在第一衬底上方的第二衬底（120），并且其中具有第二导电路径（121），其中第一导电路径和 第二导电路径彼此电连接并形成电感器（130）的电流回路（131）的一部分。

公开(公告)号：WO2017111841A1

公开(公告)日：2017-06-29

申请号：PCT/US2015/000399

申请日：2015-12-26

Applicant: INTEL CORPORATION

Inventor： RAGHUNATHAN, Vivek ,  ROY, Mihir, K. ,  MAHAJAN, Ravindranath, V.

IPC: H01S5/024 ,  G06F1/20 ,  H04B1/38

CPC classification number: G06F1/20 ,  H01S3/0408 ,  H04B1/38 ,  H04B1/385

Abstract: Embodiments are generally directed to a self-cooled laser integrated device and substrate architecture. An embodiment of a device includes a substrate or printed circuit board (PCB); a component coupled with the substrate or PCB, the component including an cooling agent on at least one side of the component; one or more laser sources, at least a first laser source of the one or more laser sources being implemented to direct laser light onto the cooling agent; and a controller to drive the laser source, wherein the cooling agent provides cooling for the component when the laser light is directed on the engineered cooling agent.

Abstract translation: 实施例通常针对自冷却激光集成器件和衬底架构。 器件的实施例包括衬底或印刷电路板（PCB）; 与所述衬底或PCB耦合的组件，所述组件在所述组件的至少一侧上包括冷却剂; 一个或多个激光源，所述一个或多个激光源中的至少第一激光源被实现为将激光引导到所述冷却剂上; 以及驱动激光源的控制器，其中，当激光被引导到工程冷却剂上时，冷却剂为部件提供冷却。

公开(公告)号：WO2014098966A1

公开(公告)日：2014-06-26

申请号：PCT/US2013/044440

申请日：2013-06-06

Applicant: INTEL CORPORATION

Inventor： ROY, Mihir, K. ,  LOTZ, Stephanie, M. ,  JEN, Wei-Lun, Kane

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2924/0002 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/1579 ,  H01L2924/2064 ,  H05K1/0313 ,  H05K1/141 ,  H05K1/142 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/467 ,  H05K2201/048 ,  H05K2201/049 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2203/016 ,  H01L2924/00

Abstract: Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic bridge. The organic bridge can have interconnect structures that allow attachment of die to be interconnected by the organic bridge. In some embodiments, the organic bridge comprises a metal routing layer, a metal pad layer and interleaved organic polymer dielectric layers but without a substrate layer. Embodiments having only a few layers may be embedded into the top layer or top few layers of the organic package substrate. Methods of manufacture are also described.

Abstract translation: 描述允许使用有机桥的多芯片互连的实施例。 在一些实施例中，有机封装衬底具有嵌入式有机桥。 有机桥可以具有允许通过有机桥连接管芯的互连结构。 在一些实施例中，有机桥包括金属布线层，金属衬垫层和交错的有机聚合物电介质层，但没有衬底层。 只有几层的实施例可以嵌入到有机封装衬底的顶层或顶层几层中。 还描述了制造方法。