中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

179 records (took 0.015 seconds)

    无机薄膜晶体管的制作方法、柔性显示装置
    1.
    发明申请
    无机薄膜晶体管的制作方法、柔性显示装置 审中-公开

    公开(公告)号：WO2018196069A1

    公开(公告)日：2018-11-01

    申请号：PCT/CN2017/085562

    申请日：2017-05-23

    Applicant: 武汉华星光电技术有限公司

    Inventor： 梁博

    IPC: H01L21/336 ,  H01L29/06 ,  H01L21/683 ,  H01L27/32

    CPC classification number: H01L21/6835 ,  H01L27/3262 ,  H01L29/0665 ,  H01L29/66772 ,  H01L2221/68345

    Abstract: 一种无机薄膜晶体管的制作方法，包括：在硬质基板（100）上依次形成P型半导体层（210）和N型半导体层（220）；在P型半导体层中形成贯穿N型半导体层的凹槽（230）；在N型半导体层上形成分别位于凹槽两侧的源极（310）和漏极（320）；通过翻转转移的方式将P型半导体层、N型半导体层、源极和漏极转移到柔性基板（400）上；在P型半导体层上依次形成栅极绝缘层（600）和栅极（700）；在栅极绝缘层上形成覆盖栅极的平坦层（800）。还提供了一种由该制作方法制作的无机薄膜晶体管的柔性显示装置。通过纳米压印的方法制备适于柔性显示制程且有良好电学性能的无机薄膜晶体管，通过设计无机薄膜晶体管的结构，获得窄沟道无机薄膜晶体管器件，并降低制程要求，节约成本。

    METHOD FOR THREE-DIMENSIONAL PACKAGING OF ELECTRONIC DEVICES
    7.
    发明申请
    METHOD FOR THREE-DIMENSIONAL PACKAGING OF ELECTRONIC DEVICES 审中-公开
    电子器件三维包装方法

    公开(公告)号：WO2013119514A1

    公开(公告)日：2013-08-15

    申请号：PCT/US2013/024685

    申请日：2013-02-05

    Applicant: GTAT CORPORATION

    Inventor： MURALI, Venkatesan ,  CHARI, Arvind ,  PRABHU, Gopal

    IPC: H01L23/48 ,  H01L23/12

    CPC classification number: H01L21/76898 ,  H01L21/2007 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2224/16

    Abstract: An interposer is fabricated from a lamina. A donor body is provided, ions are implanted into a first surface of the donor body to define a cleave plane, a temporary carrier is separably contacted to the donor body, and the lamina is cleaved from the donor body. The lamina has front surface and a back surface, with a thickness from the front surface to the back surface. A via hole is formed in the lamina, where the via hole extends through the thickness of the lamina. The temporary carrier is removed from the lamina, and the lamina may be fabricated into an interposer for three-dimensional integrated circuit packages.

    Abstract translation: 插层由薄片制成。 提供供体，离子被植入供体体的第一表面以限定劈平面，临时载体与供体本体分离接触，并且层从供体体上切下。 薄片具有前表面和后表面，其厚度从前表面到后表面。 通孔形成在层板中，通孔延伸穿过层的厚度。 将临时载体从薄片上移除，并将薄片制成三维集成电路封装的插入件。

    METHOD OF MAKING A MULTI-CHIP MODULE HAVING A REDUCED THICKNESS AND RELATED DEVICES
    8.
    发明申请
    METHOD OF MAKING A MULTI-CHIP MODULE HAVING A REDUCED THICKNESS AND RELATED DEVICES 审中-公开
    制造具有减小厚度的多芯片模块的方法及相关设备

    公开(公告)号：WO2012054169A1

    公开(公告)日：2012-04-26

    申请号：PCT/US2011/052653

    申请日：2011-09-21

    Applicant: HARRIS CORPORATION

    Inventor： REED, Thomas ,  HERNDON, David ,  NICOL, David ,  WEATHERSPOON, Michael

    IPC: H01L21/98 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H05K3/46

    CPC classification number: H01L21/563 ,  H01L21/4857 ,  H01L21/6835 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2924/14 ,  H01L2924/15788 ,  H05K3/4682 ,  H05K2201/0154 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A method of making a multi-chip module may include forming an interconnect layer stack on a sacrificial substrate. The interconnect layer stack may include patterned electrical conductor layers and a dielectric layer between adjacent patterned electrical conductor layers. The method may further include electrically coupling a first integrated circuit (IC) die in a flip chip arrangement to an uppermost patterned electrical conductor layer, and forming a first underfill dielectric layer between the first IC die and adjacent portions of the interconnect layer stack. The method further may include removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at a second integrated circuit die in a flip chip arrangement to the lowermost patterned electrical conductor layer. Still further, the method may include forming a second underfill dielectric layer between the second IC die and adjacent portions of the interconnect layer stack.

    Abstract translation: 制造多芯片模块的方法可以包括在牺牲衬底上形成互连层堆叠。 互连层堆叠可以包括图案化的导电层和相邻图案化的导电层之间的介电层。 该方法还可以包括将倒装芯片布置中的第一集成电路（IC）管芯电耦合到最上面的图案化导电体层，以及在第一IC管芯和互连层堆叠的相邻部分之间形成第一底部填充介电层。 该方法还可以包括去除牺牲基板以暴露最下图案化的导电层，并且将第二集成电路管芯以倒装芯片布置电耦合到最下图案化导电层。 此外，该方法可以包括在第二IC管芯和互连层堆叠的相邻部分之间形成第二底部填充介电层。

    METHOD FOR PRODUCING A FLEXIBLE CIRCUIT CONFIGURATION
    9.
    发明申请
    METHOD FOR PRODUCING A FLEXIBLE CIRCUIT CONFIGURATION 审中-公开
    生产柔性电路配置的方法

    公开(公告)号：WO2011138232A1

    公开(公告)日：2011-11-10

    申请号：PCT/EP2011/056783

    申请日：2011-04-28

    Applicant: CICOR MANAGEMENT AG ,  RUESS, Karin ,  FEURER, Ernst ,  HOLL, Bruno ,  KAISER, Alexander

    Inventor： FEURER, Ernst ,  HOLL, Bruno ,  KAISER, Alexander

    IPC: H05K3/00 ,  H05K3/46 ,  H01L21/48 ,  H01L21/683

    CPC classification number: H05K3/0097 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/4985 ,  H01L2221/68345 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K3/007 ,  H05K3/4682 ,  H05K2203/016 ,  H05K2203/1536 ,  H01L2924/00

    Abstract: For a method for producing a flexible circuit configuration in the form of a layer sequence of at least one insulating layer and at least one conductive layer, typically multiple insulating layers (N1, N2, N3, NF) and multiple structured conductive layers (L1, L2), the layer sequence for the flexible circuit configuration is deposited on a rigid substrate so that the adhesion of the layer sequence with respect to the substrate is less in an inner area, in which at least one, preferably multiple flexible circuit configurations are created, than in an edge area (RB) which surrounds the inner area (ZB). An intermediate layer can advantageously be deposited for this purpose in the edge area, which causes a stronger adhesion of the layer sequence over the edge area than the inner area, which is not provided with an intermediate layer.

    Abstract translation: 对于以至少一个绝缘层和至少一个导电层（通常为多个绝缘层（N1，N2，N3，NF））和多个结构化导电层（L1，N2）的层序列形式的柔性电路结构的制造方法， L2），用于柔性电路配置的层序列沉积在刚性衬底上，使得层序列相对于衬底的粘附力在内部区域中较少，其中至少一个，优选地多个柔性电路配置被创建 ，而不是围绕内部区域（ZB）的边缘区域（RB）。 中间层可以有利地沉积在边缘区域中，这使得层序列在边缘区域上比不具有中间层的内部区域更强的附着。

Patent Agency Ranking