公开(公告)号：WO2016049599A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/052497

申请日：2015-09-25

Applicant: KILOPASS TECHNOLOGY, INC.

Inventor： LUAN, Harry ,  BATEMAN, Bruce ,  AXELRAD, Valery ,  CHENG, Charlie ,  CHEVALLIER, Christophe

IPC: G11C11/00 ,  G11C11/411 ,  G11C11/419 ,  G11C11/34 ,  G11C7/12

CPC classification number: G11C11/39 ,  G11C5/14 ,  G11C11/34 ,  G11C11/4113 ,  G11C11/416 ,  G11C11/418 ,  G11C11/419 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0821 ,  H01L27/0826 ,  H01L27/1027 ,  H01L27/11 ,  H01L27/1104

Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

Abstract translation: 基于用于SRAM集成电路的晶闸管的双晶体管存储单元与操作方法一起被描述。 存储器单元可以以具有浅沟槽隔离的半导体衬底中的晶闸管与MOS和双极选择晶体管的不同组合或不具有选择晶体管来实现。 标准CMOS工艺技术可用于制造SRAM。

公开(公告)号：WO2016049594A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/052488

申请日：2015-09-25

Applicant: KILOPASS TECHNOLOGY, INC.

Inventor： LUAN, Harry ,  BATEMAN, Bruce ,  AXELRAD, Valery ,  CHENG, Charlie ,  CHEVALLIER, Christophe

IPC: G11C11/00 ,  G11C11/411 ,  G11C11/419 ,  G11C11/34 ,  G11C7/12

CPC classification number: H01L27/1104 ,  G11C11/39 ,  G11C11/41 ,  G11C11/411 ,  H01L21/8229 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0821 ,  H01L27/0826 ,  H01L27/1025 ,  H01L27/1027 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/083 ,  H01L29/0847 ,  H01L29/1004 ,  H01L29/1012 ,  H01L29/1095 ,  H01L29/66272 ,  H01L29/66386 ,  H01L29/732 ,  H01L29/742 ,  H01L29/7455

Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

Abstract translation: 基于用于SRAM集成电路的晶闸管的双晶体管存储单元及其制造方法一起被描述。 存储器单元可以以具有浅沟槽隔离的半导体衬底中的晶闸管与MOS和双极选择晶体管的不同组合或不具有选择晶体管来实现。 标准CMOS工艺技术可用于制造SRAM。

公开(公告)号：WO2016049608A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/052507

申请日：2015-09-25

Applicant: KILOPASS TECHNOLOGY, INC.

Inventor： LUAN, Harry ,  BATEMAN, Bruce ,  AXELRAD, Valery ,  CHENG, Charlie

IPC: G11C7/00

CPC classification number: H01L27/1027 ,  G06F11/1048 ,  G11C11/39 ,  G11C11/4026 ,  G11C11/406 ,  G11C11/4067 ,  G11C11/408 ,  G11C11/4094 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/1023 ,  H01L29/66121 ,  H01L29/87

Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of reducing power consumption in such arrays.

Abstract translation: 公开了使用垂直晶闸管的易失性存储器阵列以及降低这种阵列中的功率消耗的方法。

公开(公告)号：WO2016049601A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/052499

申请日：2015-09-25

Applicant: KILOPASS TECHNOLOGY, INC.

Inventor： LUAN, Harry ,  BATEMAN, Bruce ,  AXELRAD, Valery ,  CHENG, Charlie

IPC: G11C11/00 ,  H01L21/76 ,  H01L27/00

CPC classification number: H01L27/1027 ,  G06F11/1048 ,  G11C11/39 ,  G11C11/4026 ,  G11C11/406 ,  G11C11/4067 ,  G11C11/408 ,  G11C11/4094 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/1023 ,  H01L29/66121 ,  H01L29/87

Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of fabricating the array.

Abstract translation: 公开了使用垂直晶闸管的易失性存储器阵列以及制造阵列的方法。

公开(公告)号：WO2016133930A1

公开(公告)日：2016-08-25

申请号：PCT/US2016/018121

申请日：2016-02-16

Applicant: KILOPASS TECHNOLOGY, INC.

Inventor： BILL, Colin Stewart ,  LUAN, Harry

IPC: G11C11/39 ,  G11C11/56

CPC classification number: G11C11/39 ,  G11C5/06 ,  G11C5/063 ,  G11C16/0466 ,  G11C16/14 ,  H01L27/1027 ,  H01L29/7404 ,  H01L29/7436 ,  H01L29/792

Abstract: An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

Abstract translation: 描述了用于集成电路存储器阵列的MTP（许多次可编程）存储器单元。 该单元包括MTP器件和互连的晶闸管，使得MTP器件在读取或验证操作期间触发晶闸管导通。 使用数据存储单元和参考存储单元之间的阈值电压的差来确定数据存储单元中的信息。 可以为不同的存储器阵列要求构建不同的存储器单元结构。

公开(公告)号：WO2018089559A1

公开(公告)日：2018-05-17

申请号：PCT/US2017/060727

申请日：2017-11-08

Applicant: KILOPASS TECHNOLOGY, INC.

Inventor： LUAN, Harry ,  AXELRAD, Valery ,  CHENG, Charlie

IPC: H01L21/8229 ,  H01L29/66 ,  H01L27/102 ,  H01L21/76

CPC classification number: H01L27/1052 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/8229 ,  H01L27/0817 ,  H01L27/1027 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66363 ,  H01L29/66378 ,  H01L29/742 ,  H01L29/749

Abstract: Memory arrays of vertical thyristor memory cells with SiGe base layers are described. The composition of the SiGe can be constant or varied depending upon the desired characteristics of the memory cells. The memory cells allow a compact structure with desirable low voltage operations.

Abstract translation: 描述了具有SiGe基极层的垂直晶闸管存储单元的存储器阵列。 SiGe的组成可以是恒定的或根据存储器单元的期望特性而变化。 存储器单元允许具有期望的低电压操作的紧凑结构。

公开(公告)号：WO2016049590A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/052480

申请日：2015-09-25

Applicant: KILOPASS TECHNOLOGY, INC.

Inventor： LUAN, Harry ,  BATEMAN, Bruce ,  AXELRAD, Valery ,  CHENG, Charlie ,  CHEVALLIER, Christophe

IPC: G11C11/00 ,  G11C11/411 ,  G11C11/419 ,  G11C11/34 ,  G11C7/12

CPC classification number: H01L27/0623 ,  G11C11/39 ,  G11C11/4113 ,  G11C11/4116 ,  G11C11/416 ,  G11C11/419 ,  H01L21/8249 ,  H01L27/1025 ,  H01L27/1027 ,  H01L27/11 ,  H01L29/7404 ,  H01L29/7436

Abstract: A memory cell based upon thyristors for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. Special circuitry provides lowered power consumption during standby.

Abstract translation: 基于用于SRAM集成电路的晶闸管的存储单元与其制造方法一起被描述。 存储器单元可以在具有浅沟槽隔离的半导体衬底中的晶闸管的MOS和双极选择晶体管的不同组合中实现，或者不具有选择晶体管。 标准CMOS工艺技术可用于制造SRAM。 特殊电路在待机期间提供降低的功耗。

公开(公告)号：WO2016049581A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/052468

申请日：2015-09-25

Applicant: KILOPASS TECHNOLOGY, INC.

Inventor： LUAN, Harry ,  BATEMAN, Bruce ,  AXELRAD, Valery ,  CHENG, Charlie ,  CHEVALLIER, Christophe

IPC: G11C11/00 ,  G11C11/411 ,  G11C7/12 ,  G11C11/34 ,  G11C11/419

CPC classification number: H01L27/0623 ,  G11C11/39 ,  G11C11/4113 ,  G11C11/4116 ,  G11C11/416 ,  G11C11/419 ,  H01L21/8249 ,  H01L27/1025 ,  H01L27/1027 ,  H01L27/11 ,  H01L29/7404 ,  H01L29/7436

Abstract: A memory cell based upon thyristors for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. Special circuitry provides lowered power consumption during standby.

Abstract translation: 基于用于SRAM集成电路的晶闸管的存储单元与其制造方法一起被描述。 存储器单元可以以具有浅沟槽隔离的半导体衬底中的晶闸管与MOS和双极选择晶体管的不同组合或不具有选择晶体管来实现。 标准CMOS工艺技术可用于制造SRAM。 特殊电路在待机期间提供降低的功耗。

公开(公告)号：WO2017139286A1

公开(公告)日：2017-08-17

申请号：PCT/US2017/016865

申请日：2017-02-07

Applicant: KILOPASS TECHNOLOGY, INC.

Inventor： CHENG, Charlie ,  AXELRAD, Valery ,  LUAN, Harry

IPC: H01L27/08 ,  H01L27/102

CPC classification number: H01L27/1027 ,  G11C11/39 ,  H01L21/02271 ,  H01L21/221 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/32053 ,  H01L21/8229 ,  H01L23/53209 ,  H01L23/53242 ,  H01L27/0817 ,  H01L27/1023 ,  H01L27/10802 ,  H01L28/00 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0839 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66363 ,  H01L29/74 ,  H01L29/87

Abstract: Apparatus and methods for reducing minority carriers in a memory array are described herein. Minority carriers diffuse between ON cells and OFF cells, causing disturbances during write operation as well as reducing the retention lifetime of the cells. Minority Carrier Lifetime Killer (MCLK) region architectures are described for vertical thyristor memory arrays with insulation trenches. These MCLK regions encourage recombination of minority carriers. In particular, MCLK regions formed by conductors embedded along the cathode line of a thyristor array, as well as dopant MCLK regions are described, as well as methods for manufacturing thyristor memory cells with MCLK regions.

Abstract translation: 这里描述了用于减少存储器阵列中的少数载流子的装置和方法。 少数载流子在ON单元和OFF单元之间扩散，在写操作期间造成干扰并且减少单元的保持寿命。 描述了具有绝缘沟槽的垂直晶闸管存储器阵列的少数载流子寿命终止器（MCLK）区域架构。 这些MCLK区域鼓励少数载流子的重组。 特别地，描述了由沿着晶闸管阵列的阴极线嵌入的导体形成的MCLK区域以及掺杂剂MCLK区域，以及用于制造具有MCLK区域的晶闸管存储器单元的方法。

公开(公告)号：WO2016049606A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/052505

申请日：2015-09-25

Applicant: KILOPASS TECHNOLOGY, INC.

Inventor： LUAN, Harry ,  BATEMAN, Bruce ,  AXELRAD, Valery ,  CHENG, Charlie

IPC: G11C11/34

CPC classification number: H01L27/1027 ,  G06F11/1048 ,  G11C11/39 ,  G11C11/4026 ,  G11C11/406 ,  G11C11/4067 ,  G11C11/408 ,  G11C11/4094 ,  H01L21/76 ,  H01L21/76224 ,  H01L27/1023 ,  H01L29/66121 ,  H01L29/87

Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read, write, retain and refresh data stored therein.

Abstract translation: 公开了使用垂直晶闸管的易失性存储器阵列以及操作阵列以读取，写入，保留和刷新存储在其中的数据的方法。