公开(公告)号：WO2014026006A3

公开(公告)日：2014-02-13

申请号：PCT/US2013/054144

申请日：2013-08-08

Applicant: MARVELL WORLD TRADE LTD. ,  SUTARDJA, Sehat

Inventor： SUTARDJA, Sehat

IPC: G01D5/241 ,  H02K11/00

Abstract: A motor having a rotor, the rotor including a first metal plate having a first size and a second metal plate having a second size arranged on a first surface associated with the rotor. The first metal plate and the second metal plate are arranged adjacent to each other at a predetermined distance from an axis of rotation of the rotor. The first surface rotates perpendicularly about the axis in response to the rotor being rotated about the axis. A stator includes a third metal plate arranged on a second surface associated with the stator. The third metal plate is arranged on the second surface at the predetermined distance from the axis. The second surface is parallel to the first surface and faces the first surface.

公开(公告)号：WO2009079096A1

公开(公告)日：2009-06-25

申请号：PCT/US2008/081442

申请日：2008-10-28

Applicant: MARVELL WORLD TRADE LTD. ,  SUTARDJA, Sehat

Inventor： SUTARDJA, Sehat

IPC: H03F3/45 ,  H03F1/08 ,  H03F3/30

CPC classification number: H03F1/086 ,  H03F3/3001 ,  H03F3/45179 ,  H03F2200/153 ,  H03F2203/30033 ,  H03F2203/45028 ,  H03F2203/45318 ,  H03F2203/45424

Abstract: A multi-stage Class AB amplifier system comprises a first Class AB amplifier circuit (20) that receives an input signal. A bias circuit (24) receives an output of the first Class AB amplifier circuit (20). A second Class AB amplifier circuit (28) communicates with the bias circuit (24) and generates an output signal. A common-mode feedback circuit (30) generates a feedback signal based on the output signal.

Abstract translation: 多级AB类放大器系统包括接收输入信号的第一AB类放大器电路（20）。 偏置电路（24）接收第一AB类放大器电路（20）的输出。 第二AB类放大器电路（28）与偏置电路（24）通信并产生输出信号。 共模反馈电路（30）基于输出信号产生反馈信号。

公开(公告)号：WO2009048486A1

公开(公告)日：2009-04-16

申请号：PCT/US2008/004439

申请日：2008-04-04

Applicant: MARVELL WORLD TRADE LTD. ,  SUTARDJA, Sehat ,  SU, Jason, T. ,  CHEN, Hong-Yi ,  SHEU, Jason ,  TJENG, Jensen

Inventor： SUTARDJA, Sehat ,  SU, Jason, T. ,  CHEN, Hong-Yi ,  SHEU, Jason ,  TJENG, Jensen

IPC: G06F12/08 ,  G11C7/12 ,  G06F9/38

CPC classification number: G06F12/0882 ,  G06F9/30054 ,  G06F9/30058 ,  G06F9/3804 ,  G06F9/3844 ,  G11C7/06 ,  G11C7/1018 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/12 ,  G11C7/22 ,  G11C2207/2245 ,  G11C2207/2281 ,  Y02D10/13

Abstract: A processor includes a cache memory that has an array, word lines, and bit lines. A control module accesses cells of the array during access cycles to access instructions stored in the cache memory. The control module performs one of a first discrete read and a first sequential read to access instructions in a first set of cells of the array that are connected to a first word line and selectively performs one of a second discrete read and a second sequential read based on a branch instruction to access instructions in a second set of cells of the array that are connected to a second word line. The second word line is different than the first word line.

Abstract translation: 处理器包括具有阵列，字线和位线的高速缓冲存储器。 控制模块在访问周期期间访问阵列的单元以访问存储在高速缓冲存储器中的指令。 控制模块执行第一离散读取和第一顺序读取之一以访问连接到第一字线的阵列的第一组单元中的指令，并且选择性地执行第二离散读取和第二顺序读取之一 在分支指令上访问连接到第二字线的阵列的第二组单元格中的指令。 第二个字线与第一个字线不同。

公开(公告)号：WO2008130593A1

公开(公告)日：2008-10-30

申请号：PCT/US2008/004952

申请日：2008-04-17

Applicant: MARVELL WORLD TRADE LTD. ,  SUTARDJA, Sehat

Inventor： SUTARDJA, Sehat

IPC: G06F13/38 ,  G06F13/40 ,  G06F3/06

CPC classification number: G06F13/385 ,  G06F3/061 ,  G06F3/0658 ,  G06F3/0683 ,  G06F13/4022 ,  G06F2213/0038

Abstract: A system-on-chip (SOC) includes N physical layer (PHY) devices and a first host controller. The N PHY devices communicate with N peripheral devices, respectively, where N is an integer greater than 1. The host controller communicates with a host and is integrated with the N PHY devices in an integrated circuit (IC). The host controller is directly coupled to the N PHY devices and is configured to control the N peripheral devices. The host controller includes a selector that selectively connects one of the N PHY devices to the host controller. The N PHY devices and the N peripheral devices implement a Serial Advanced Technology Attachment (SATA) interface.

Abstract translation: 片上系统（SOC）包括N个物理层（PHY）设备和第一主机控制器。 N PHY设备分别与N个外围设备进行通信，其中N是大于1的整数。主机控制器与主机通信并且与集成电路（IC）中的N个PHY设备集成。 主机控制器直接耦合到N个PHY设备，并被配置为控制N个外围设备。 主机控制器包括选择器，其将N个PHY设备之一选择性地连接到主机控制器。 N PHY设备和N个外围设备实现了串行高级技术附件（SATA）接口。

公开(公告)号：WO2008115468A2

公开(公告)日：2008-09-25

申请号：PCT/US2008/003491

申请日：2008-03-17

Applicant: MARVELL WORLD TRADE LTD. ,  SUTARDJA, Sehat

Inventor： SUTARDJA, Sehat

IPC: H01L23/482 ,  H01L27/092

CPC classification number: H01L23/50 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/142 ,  H01L23/367 ,  H01L23/4824 ,  H01L23/49541 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/16 ,  H01L24/40 ,  H01L24/49 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/4918 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit comprises N plane-like metal layers, where N is an integer greater than one. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively, where M is an integer greater than one. The first plane-like metal layer and the N plane-like metal layers are located in separate planes. At least two of a first source, a first drain and a second source communicate with at least two of the N plane-like metal layers. A first gate is arranged between the first source and the first drain. A second gate is arranged between the first drain and the second source. The first and second gates define alternating first and second regions in the first drain, and wherein the first and second gates are arranged farther apart in the first regions than in the second regions.

Abstract translation: 集成电路包括N个平面状金属层，其中N是大于1的整数。 第一平面状金属层包括分别与N平面状金属层连通的M个接触部，其中M是大于1的整数。 第一平面状金属层和N平面状金属层位于分开的平面中。 第一源，第一漏极和第二源中的至少两个与N个平面状金属层中的至少两个连通。 第一栅极布置在第一源极和第一漏极之间。 第二栅极布置在第一漏极和第二源极之间。 第一和第二栅极在第一漏极中限定交替的第一和第二区域，并且其中第一和第二栅极在第一区域中比在第二区域中更远地布置。

公开(公告)号：WO2008083180A2

公开(公告)日：2008-07-10

申请号：PCT/US2007/088866

申请日：2007-12-26

Applicant: MARVELL WORLD TRADE LTD. ,  SUTARDJA, Sehat ,  KRISHNAMOORTHY, Ravishanker

Inventor： SUTARDJA, Sehat ,  KRISHNAMOORTHY, Ravishanker

IPC: H01L29/78 ,  H01L21/336 ,  H01L27/088

CPC classification number: H01L27/0207 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7835

Abstract: A Metal Oxide Semiconductor (MOS) device formed on a substrate and a method for forming the MOS device. The MOS device includes a drain region, a gate region surrounding the drain region, source regions arranged around the gate region and across from the drain region, and bulk regions arranged around the gate region and separating the source regions. The gate region is formed in a loop around the drain region. In this manner, the on-resistance (Ron) of a MOS device is decreased without also increasing the area of the MOS device.

Abstract translation: 在衬底上形成的金属氧化物半导体（MOS）器件以及用于形成MOS器件的方法。 MOS器件包括漏极区域，围绕漏极区域的栅极区域，布置在栅极区域周围并且与漏极区域相对的源极区域以及布置在栅极区域周围并分离源极区域的体区域。 栅极区域形成为围绕漏极区域的环路。 以这种方式，MOS器件的导通电阻（Ron）减小而不增加MOS器件的面积。

公开(公告)号：WO2008005112A3

公开(公告)日：2008-01-10

申请号：PCT/US2007/011880

申请日：2007-05-18

Applicant: MARVELL WORLD TRADE LTD. ,  SUTARDJA, Sehat

Inventor： SUTARDJA, Sehat

IPC: G05F1/00 ,  G01R31/28

Abstract: A testing system comprises a configurable integrated circuit that selectively communicates with one or more of N external impedances, that has M predetermined configurations that are selected based on an electrical characteristic of the one or more of the N external impedances, where N and M are integers greater than one. The configurable integrated circuit generates a selected one of M discrete values of an output characteristic of the configurable integrated circuit based on the selected one of the M predetermined configurations. An integrated circuit is tested in accordance with an output of the configurable integrated circuit.

公开(公告)号：WO2016196798A1

公开(公告)日：2016-12-08

申请号：PCT/US2016/035526

申请日：2016-06-02

Applicant: MARVELL WORLD TRADE LTD. ,  SUTARDJA, Sehat ,  LEE, Winston ,  LEE, Peter ,  CHANG, Runzi

Inventor： SUTARDJA, Sehat ,  LEE, Winston ,  LEE, Peter ,  CHANG, Runzi

IPC: H01L21/8234 ,  H01L27/105 ,  H01L27/108

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/456

Abstract: Systems and methods are provided for using and manufacturing a semiconductor device. A semiconductor device comprises an array of transistors, wherein each respective transistor in at least some of the transistors in the array of transistors (i) is positioned adjacent to a respective first neighboring transistor and a respective second neighboring transistor in the array of transistors, (ii) has a source region that shares a first contact with a source region of the respective first neighboring transistor, and (iii) has a drain region that shares a second contact with a drain region of the respective second neighboring transistor.

Abstract translation: 提供了使用和制造半导体器件的系统和方法。 半导体器件包括晶体管阵列，其中晶体管阵列（i）中的至少一些晶体管中的每个相应的晶体管位于晶体管阵列中相应的第一相邻晶体管和相应的第二相邻晶体管附近（ ii）具有与相应的第一相邻晶体管的源极区域共享第一接触的源极区域，以及（iii）具有与相应的第二相邻晶体管的漏极区域共享第二接触的漏极区域。

公开(公告)号：WO2014130075A1

公开(公告)日：2014-08-28

申请号：PCT/US2013/051403

申请日：2013-07-19

Applicant: MARVELL WORLD TRADE LTD. ,  SUTARDJA, Sehat ,  LI, Kan ,  LEONG, Poh Boon

Inventor： SUTARDJA, Sehat ,  LI, Kan ,  LEONG, Poh Boon

IPC: H03F1/08 ,  H03F3/24 ,  H03F1/34 ,  H03F1/56 ,  H03F3/193

CPC classification number: H03F1/083 ,  H03F1/34 ,  H03F1/56 ,  H03F3/193 ,  H03F3/245 ,  H03F2200/121 ,  H03F2200/138 ,  H03F2200/147 ,  H03F2200/153 ,  H03F2200/168 ,  H03F2200/541

Abstract: An amplifier circuit (1000) amplifies a signal for wireless transmission. A feedback circuit (208), including a capacitor, is coupled to the amplifier circuit. Components of the feedback circuit (208) are selected based on a feedback factor such that an input impedance (Z input) to the amplifier circuit (1000) has a same impedance characteristic as a feedback circuit impedance of the feedback circuit (208).

Abstract translation: 放大器电路（1000）放大用于无线传输的信号。 包括电容器的反馈电路（208）耦合到放大器电路。 基于反馈因子来选择反馈电路（208）的组件，使得到放大器电路（1000）的输入阻抗（Z输入）具有与反馈电路（208）的反馈电路阻抗相同的阻抗特性。

公开(公告)号：WO2013078311A1

公开(公告)日：2013-05-30

申请号：PCT/US2012/066257

申请日：2012-11-21

Applicant: MARVELL WORLD TRADE LTD. ,  SUTARDJA, Pantas ,  SUTARDJA, Sehat

Inventor： SUTARDJA, Pantas ,  SUTARDJA, Sehat

IPC: G06F1/08 ,  G06F1/32 ,  H03L7/00

CPC classification number: H03K3/02 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A system including a plurality of amplifiers configured to generate a clock signal having a frequency. The clock signal is input to a processor. The amplifiers are connected in series. An output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers. Each of the amplifiers has a transconductance. A frequency adjustment module is configured to adjust, based on an activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the amplifiers.

Abstract translation: 一种包括配置成产生具有频率的时钟信号的多个放大器的系统。 时钟信号被输入到处理器。 放大器串联。 最后一个放大器的输出被反馈到第一个放大器的输入端。 每个放大器都有跨导。 频率调整模块被配置为通过调节放大器的跨导来调整基于处理器的活动电平的时钟信号的频率。