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    METHODS FOR NANOSTRUCTURE DOPING
    1.
    发明申请
    METHODS FOR NANOSTRUCTURE DOPING 审中-公开
    用于纳米结构的方法

    公开(公告)号：WO2007038164A2

    公开(公告)日：2007-04-05

    申请号：PCT/US2006036738

    申请日：2006-09-21

    Applicant: NANOSYS INC ,  PAN YAOLING ,  CHEN JIAN ,  LEON FRANCISCO ,  MOSTARSHED SHAHRIAR ,  ROMANO LINDA T ,  SAHI VIJENDRA ,  STUMBO DAVID P

    Inventor： PAN YAOLING ,  CHEN JIAN ,  LEON FRANCISCO ,  MOSTARSHED SHAHRIAR ,  ROMANO LINDA T ,  SAHI VIJENDRA ,  STUMBO DAVID P

    IPC: H01L29/06 ,  H01L21/225

    CPC classification number: H01L29/0665 ,  B81C1/00698 ,  B81C2201/0173 ,  B82Y10/00 ,  H01L21/2256 ,  H01L21/268 ,  H01L29/0673

    Abstract: Methods of doping nanostructures, such as nanowires, are disclosed. The methods provide a variety of approaches for improving existing methods of doping nanostructures. The embodiments include the use of a sacrificial layer to promote uniform dopant distribution within a nanostructure during post-nanostructure synthesis doping. In another embodiment, a high temperature environment is used to anneal nanostructure damage when high energy ion implantation is used. In another embodiment rapid thermal annealing is used to drive dopants from a dopant layer on a nanostructure into the nanostructure. In another embodiment a method for doping nanowires on a plastic substrate is provided that includes depositing a dielectric stack on a plastic substrate to protect the plastic substrate from damage during the doping process. An embodiment is also provided that includes selectively using high concentrations of dopant materials at various times in synthesizing nanostructures to realize novel crystallographic structures within the resulting nanostructure.

    Abstract translation: 公开了掺杂纳米结构的方法，例如纳米线。 该方法提供了改进现有的纳米结构掺杂方法的各种方法。 实施例包括在后纳米结构合成掺杂期间使用牺牲层来促进纳米结构内的均匀掺杂剂分布。 在另一个实施例中，当使用高能离子注入时，使用高温环境退火纳米结构损伤。 在另一个实施方案中，使用快速热退火来将掺杂剂从纳米结构上的掺杂剂层驱动到纳米结构中。 在另一个实施例中，提供了一种在塑料衬底上掺杂纳米线的方法，其包括在塑料衬底上沉积电介质叠层以保护塑料衬底免于在掺杂过程期间损坏。 还提供了一种实施方案，其包括在合成纳米结构中在不同时间选择性地使用高浓度的掺杂剂材料，以在所得纳米结构内实现新的晶体结构。

    CONTACT DOPING AND ANNEALING SYSTEMS AND PROCESSES FOR NANOWIRE THIN FILMS
    3.
    发明申请
    CONTACT DOPING AND ANNEALING SYSTEMS AND PROCESSES FOR NANOWIRE THIN FILMS 审中-公开
    联系DOPING和退火系统和纳米薄膜的工艺

    公开(公告)号：WO2006057818A3

    公开(公告)日：2008-01-03

    申请号：PCT/US2005040710

    申请日：2005-11-10

    Applicant: NANOSYS INC ,  PAN YAOLING ,  STUMBO DAVID P

    Inventor： PAN YAOLING ,  STUMBO DAVID P

    IPC: B82B1/00 ,  B82B3/00 ,  H01L21/00

    CPC classification number: H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/7606 ,  H01L29/78696 ,  Y10S977/901 ,  Y10S977/963

    Abstract: Embodiments of the present invention are provided for improved contact doping and annealing systems and processes. In embodiments, a plasma ion immersion implantation (PIII) process is used for contact doping of nanowires and other nanoelement based thin film devices. According to further embodiments of the present invention, pulsed laser annealing using laser energy at relatively low laser fluences below about 100 mJ/cm 2 (e.g., less than about 50 mJ/cm 2 , e.g., between about 2 and 18 mJ/cm 2 ) is used to anneal nanowire and other nanoelement-based devices on substrates, such as low temperature flexible substrates, e.g., plastic substrates.

    Abstract translation: 提供本发明的实施例用于改进的接触掺杂和退火系统和工艺。 在实施例中，等离子体离子浸没注入（PIII）工艺用于纳米线和其它基于纳米元件的薄膜器件的接触掺杂。 根据本发明的另外的实施例，使用在低于约100mJ / cm 2（例如小于约50mJ / cm 2）的较低激光能量密度的激光能量进行脉冲激光退火， SUP>，例如约2和18mJ / cm 2之间）用于退火衬底上的纳米线和其它基于纳米元件的器件，例如低温柔性衬底，例如塑料衬底。

    FULLY INTEGRATED ORGANIC LAYERED PROCESSES FOR MAKING PLASTIC ELECTRONICS BASED ON CONDUCTIVE POLYMERS AND SEMICONDUCTOR NANOWIRES
    4.
    发明申请
    FULLY INTEGRATED ORGANIC LAYERED PROCESSES FOR MAKING PLASTIC ELECTRONICS BASED ON CONDUCTIVE POLYMERS AND SEMICONDUCTOR NANOWIRES 审中-公开
    基于导电聚合物和半导体纳米粒子制备塑料电子的全集成有机层状工艺

    公开(公告)号：WO2006124055A2

    公开(公告)日：2006-11-23

    申请号：PCT/US2005034394

    申请日：2005-09-22

    Applicant: NANOSYS INC ,  PAN YAOLING ,  LEON FRANCISCO A ,  STUMBO DAVID P

    Inventor： PAN YAOLING ,  LEON FRANCISCO A ,  STUMBO DAVID P

    IPC: H01L29/08

    CPC classification number: H01L51/0545 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0035 ,  H01L51/0037 ,  H01L51/0048 ,  H01L51/0049 ,  H01L51/0541 ,  H01L51/0566 ,  H01L51/4253 ,  H01L51/4266 ,  Y02E10/549 ,  Y02P70/521 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/764

    Abstract: The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; deposing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; deposing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; deposing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones on the source and drain regions.

    Abstract translation: 本发明涉及使用并入和/或设置在导电聚合物层附近的纳米线（或其他纳米结构，例如纳米带，纳米管等）的薄膜晶体管，以及用于生产这种晶体管的生产可扩展方法。 特别地，公开了包含导电聚合材料如聚苯胺（PANI）或聚吡咯（PPY）和一个或多个纳米线的复合材料，其中并入其中。 还提供了几种纳米线TFT制造方法，其在一个示例性实施例中包括提供器件衬底; 在器件衬底上放置第一导电聚合物材料层; 限定所述导电聚合物层中的一个或多个栅极接触区域; 在所述导电聚合物层上以足够的纳米线密度去除多个纳米线以实现工作电流水平; 在所述多个纳米线上沉积第二导电聚合物材料层; 以及在所述第二导电聚合物材料层中形成源极和漏极接触区域，从而提供与所述多个纳米线的电连接性，由此所述纳米线形成在所述源极和漏极区域上的相应长度之间的长度的沟道。

    METHOD, SYSTEM, AND APPARATUS FOR GATING CONFIGURATIONS AND IMPROVED CONTACTS IN NANOWIRE-BASED ELECTRONIC DEVICES
    6.
    发明申请
    METHOD, SYSTEM, AND APPARATUS FOR GATING CONFIGURATIONS AND IMPROVED CONTACTS IN NANOWIRE-BASED ELECTRONIC DEVICES 审中-公开
    用于在纳米级电子设备中进行配置和改进联系的方法，系统和设备

    公开(公告)号：WO2007030126A9

    公开(公告)日：2007-05-18

    申请号：PCT/US2005037237

    申请日：2005-10-14

    Applicant: NANOSYS INC ,  MOSTARSHED SHAHRIAR ,  CHEN JIAN ,  LEON FRANCISCO ,  PAN YAOLING ,  ROMANO LINDA T

    Inventor： MOSTARSHED SHAHRIAR ,  CHEN JIAN ,  LEON FRANCISCO ,  PAN YAOLING ,  ROMANO LINDA T

    IPC: H01L29/76

    CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

    Abstract: Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

    Abstract translation: 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

    METHOD, SYSTEM, AND APPARATUS FOR GATING CONFIGURATIONS AND IMPROVED CONTACTS IN NANOWIRE-BASED ELECTRONIC DEVICES
    7.
    发明申请
    METHOD, SYSTEM, AND APPARATUS FOR GATING CONFIGURATIONS AND IMPROVED CONTACTS IN NANOWIRE-BASED ELECTRONIC DEVICES 审中-公开
    用于在纳米级电子设备中进行配置和改进联系的方法，系统和设备

    公开(公告)号：WO2007030126A3

    公开(公告)日：2009-04-16

    申请号：PCT/US2005037237

    申请日：2005-10-14

    Applicant: NANOSYS INC ,  MOSTARSHED SHAHRIAR ,  CHEN JIAN ,  LEON FRANCISCO ,  PAN YAOLING ,  ROMANO LINDA T

    Inventor： MOSTARSHED SHAHRIAR ,  CHEN JIAN ,  LEON FRANCISCO ,  PAN YAOLING ,  ROMANO LINDA T

    IPC: H01L29/775

    CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

    Abstract: Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one snowier; a gate contact is positioned along part of the length of the snowier, and a dielectric material layer is between the gate contact and the at least one snowier. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the snowier length. In another aspect, an electronic device includes a snowier having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the snowier along a portion of the length of the snowier. A second gate region is positioned along the length of the snowier between the snowier and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the snowier at respective exposed portions of the semiconductor core.

    Abstract translation: 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子设备包括至少一个雪地; 栅极接触沿着雪的长度的一部分定位，并且介电材料层位于栅极接触和至少一个雪层之间。 源触点和/或漏极触点的至少一部分沿着雪长度与栅极触点重叠。 另一方面，电子设备包括具有由绝缘壳层包围的半导体芯体的雪地机。 环形的第一栅极区域沿着雪橇长度的一部分包围雪橇。 第二栅极区域沿雪层和衬底之间的雪层的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到雪的半导体芯。

    NANOWIRE VARACTOR DIODE AND METHODS OF MAKING SAME
    8.
    发明申请
    NANOWIRE VARACTOR DIODE AND METHODS OF MAKING SAME 审中-公开
    纳米级变压器二极管及其制造方法

    公开(公告)号：WO2005112122A2

    公开(公告)日：2005-11-24

    申请号：PCT/US2005008891

    申请日：2005-03-17

    Applicant: NANOSYS INC ,  STUMBO DAVID ,  CHEN JIAN ,  HEALD DAVID ,  PAN YAOLING

    Inventor： STUMBO DAVID ,  CHEN JIAN ,  HEALD DAVID ,  PAN YAOLING

    IPC: H01L29/06 ,  H01L29/93

    CPC classification number: B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/93 ,  Y10S977/762

    Abstract: A nanowire varactor diode and methods of making the same are disclosed. The structure comprises a coaxial capacitor running the length of the semiconductor nanowire. In one embodiment, a semiconductor nanowire of a first conductivity type is deposited on a substrate. An insulator is formed on at least a portion of the nanowire's surface. A region of the nanowire is doped with a second conductivity type material. A first electrical contact is formed on at least part of the insulator and the doped region. A second electrical contact is formed on a non-doped potion of the nanowire. During operation, the conductivity type at the surface of the nanowire inverts and a depletion region is formed upon application of a voltage to the first and second electrical contacts. The varactor diode thereby exhibits variable capacitance as a function of the applied voltage.

    Abstract translation: 公开了一种纳米线变容二极管及其制造方法。 该结构包括运行半导体纳米线长度的同轴电容器。 在一个实施例中，第一导电类型的半导体纳米线沉积在衬底上。 在纳米线表面的至少一部分上形成绝缘体。 纳米线的区域掺杂有第二导电类型的材料。 在绝缘体和掺杂区域的至少一部分上形成第一电接触。 在纳米线的非掺杂药液上形成第二电接触。 在操作期间，纳米线表面的导电类型反转，并且在向第一和第二电触点施加电压时形成耗尽区。 因此，变容二极管作为施加电压的函数呈现可变电容。

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