公开(公告)号：WO2013071176A3

公开(公告)日：2013-10-17

申请号：PCT/US2012064536

申请日：2012-11-09

Applicant: QUALCOMM INC

Inventor： LI XIA ,  ZHU XIAOCHUN ,  KANG SEUNG H ,  KIM JUNG PILL ,  HSU WAH NAM ,  KIM TAEHYUN ,  LEE KANGHO

IPC: G11C11/16 ,  H01L29/82

CPC classification number: G11C11/161 ,  G11C8/16 ,  G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L43/08

Abstract: A two-transistor one-MTJ (2T1MTJ) three port structure includes two separate pin layer structures coupled to one free layer structure. The pin layer structures may include an anti-ferromagnetic layer (AFM) layer coupled to a pin layer. The free layer structure includes free layer coupled to a barrier layer and a cap layer. The free layer structure may include a thin barrier layer coupled to each of the pin layer stacks. The three port MTJ structure provides separate write and read paths which improve read sensing margin without increasing write voltage or current. The three port MTJ structure may be fabricated with a simple two step MTJ etch process.

Abstract translation: 双晶体管单MTJ（2T1MTJ）三端口结构包括耦合到一个自由层结构的两个分离的引脚层结构。 引脚层结构可以包括耦合到引脚层的反铁磁层（AFM）层。 自由层结构包括耦合到阻挡层和帽层的自由层。 自由层结构可以包括耦合到每个引脚层堆叠的薄阻挡层。 三端口MTJ结构提供独立的写入和读取路径，这些路径在不增加写入电压或电流的情况下提高读取感测裕度。 三端口MTJ结构可以用简单的两步MTJ刻蚀工艺制造。

公开(公告)号：WO2012019135A3

公开(公告)日：2012-03-29

申请号：PCT/US2011046811

申请日：2011-08-05

Applicant: QUALCOMM INC ,  LI XIA ,  ZHU XIAOCHUN ,  KANG SEUNG H

Inventor： LI XIA ,  ZHU XIAOCHUN ,  KANG SEUNG H

IPC: H01L27/22 ,  B82Y25/00 ,  H01L43/08 ,  H01L43/12

CPC classification number: H01L43/12 ,  B82Y10/00 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08

Abstract: A semiconductor device includes a magnetic tunnel junction (MTJ) storage element configured to be disposed in a common interlayer metal dielectric (IMD) layer with a logic element. Cap layers separate the common IMD layer from a top and bottom IMD layer. Top and bottom electrodes are coupled to the MTJ storage element. Metal connections to the electrodes are formed in the top and bottom IMD layers respectively through vias in the separating cap layers. Alternatively, the separating cap layers are recessed and the bottom electrodes are embedded, such that direct contact to metal connections in the bottom IMD layer is established. Metal connections to the top electrode in the common IMD layer are enabled by isolating the metal connections from the MTJ storage elements with metal islands and isolating caps.

Abstract translation: 一种半导体器件包括被配置为设置在具有逻辑元件的公共层间金属电介质（IMD）层中的磁性隧道结（MTJ）存储元件。 盖层将普通IMD层与顶部和底部IMD层分开。 顶部和底部电极连接到MTJ存储元件。 与电极的金属连接分别通过分离帽层中的通孔形成在顶部和底部IMD层中。 可选地，分离盖层凹入并且底部电极被嵌入，从而建立与底部IMD层中的金属连接的直接接触。 通过将金属连接与MTJ存储元件与金属岛和隔离帽隔离，可以实现与公共IMD层中的顶部电极的金属连接。

公开(公告)号：WO2010120918A3

公开(公告)日：2011-01-20

申请号：PCT/US2010031080

申请日：2010-04-14

Applicant: QUALCOMM INC ,  ZHU XIAOCHUN ,  NOWAK MATTHEW ,  LI XIA ,  KANG SEUNG H

Inventor： ZHU XIAOCHUN ,  NOWAK MATTHEW ,  LI XIA ,  KANG SEUNG H

IPC: H01L27/115 ,  G11B5/39 ,  G11C11/15

CPC classification number: H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  H01F10/3254 ,  H01F10/3272 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided.

Abstract translation: 公开了磁隧道结（MTJ）及其形成方法。 被钉扎层设置在MTJ中，使得当提供在磁随机存取存储器（MRAM）位单元中时，MTJ的自由层可以耦合到存取晶体管的漏极。 该结构改变写入电流流动方向，以使MTJ的写入电流特性与使用MTJ的MRAM位单元的写入电流供应能力对准。 结果，可以提供更多的写入电流以将MTJ从并行（P）切换到反并行（AP）状态。 在钉扎层上提供反铁磁材料（AFM）层以固定钉扎层的磁化强度。 为了提供足够的用于沉积AFM层以确保钉扎层磁化的区域，提供了具有大于自由层的自由层表面积的钉扎层表面积的钉扎层。

公开(公告)号：WO2010101860A3

公开(公告)日：2010-11-11

申请号：PCT/US2010025834

申请日：2010-03-02

Applicant: QUALCOMM INC ,  LEE KANGHO ,  KANG SEUNG H ,  ZHU XIAOCHUN

Inventor： LEE KANGHO ,  KANG SEUNG H ,  ZHU XIAOCHUN

IPC: G11C11/16

CPC classification number: H01L43/08 ,  G06F17/5068 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  H01L43/02 ,  H01L43/12

Abstract: Systems and methods to reduce source loading effects in STT-MRAM are disclosed. In a particular embodiment, a method includes determining a switching current ratio of a magnetic tunnel junction (MTJ) structure that enables stable operation of a memory cell. The memory cell includes the MTJ structure serially coupled to an access transistor. The method also includes modifying an offset magnetic field that is incident to a free layer of the MTJ structure. The modified offset magnetic field causes the MTJ structure to exhibit the switching current ratio.

Abstract translation: 公开了减少STT-MRAM中的源负载效应的系统和方法。 在特定实施例中，一种方法包括确定使得能够稳定地操作存储器单元的磁性隧道结（MTJ）结构的开关电流比。 存储单元包括串行耦合到存取晶体管的MTJ结构。 该方法还包括修改入射到MTJ结构的自由层的偏移磁场。 改进的偏移磁场使MTJ结构呈现开关电流比。

公开(公告)号：WO2016022210A3

公开(公告)日：2016-03-31

申请号：PCT/US2015035175

申请日：2015-06-10

Applicant: QUALCOMM INC

Inventor： CHEN WEI-CHUAN ,  ZHU XIAOCHUN ,  LI XIA ,  LU YU ,  PARK CHANDO ,  KANG SEUNG HYUK

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A perpendicular magnetic tunnel junction (pMTJ) device (500) includes a perpendicular reference layer (314), a tunnel barrier layer (310) on a surface of the perpendicular reference layer, and a perpendicular free layer (308) on a surface of the tunnel barrier layer. The pMTJ device also includes a dielectric passivation layer (312) on the tunnel barrier layer and surrounding the perpendicular free layer. The pMTJ device further includes a high permeability material (406) on the dielectric passivation layer that is configured to be magnetized by the perpendicular reference layer and to provide a stray field to the perpendicular free layer that compensates for a stray field from the perpendicular reference layer.

Abstract translation: 垂直磁隧道结（pMTJ）装置（500）包括垂直参考层（314），在垂直参考层的表面上的隧道势垒层（310）和在垂直参考层的表面上的垂直自由层（308） 隧道势垒层。 pMTJ器件还包括在隧道势垒层上并围绕垂直自由层的介电钝化层（312）。 pMTJ器件还包括介电钝化层上的高磁导率材料（406），其配置为被垂直参考层磁化，并且向垂直自由层提供杂散场，该杂散场补偿来自垂直参考层的杂散场 。

公开(公告)号：WO2013119846A3

公开(公告)日：2013-12-05

申请号：PCT/US2013025191

申请日：2013-02-07

Applicant: QUALCOMM INC

Inventor： LI XIA ,  WU WENQING ,  KIM JUNG PILL ,  ZHU XIAOCHUN ,  KANG SEUNG H ,  MADALA RAGHU SAGAR ,  YUEN KENDRICK H

IPC: G11C11/16 ,  G11C11/56 ,  H01L27/22

CPC classification number: G11C11/16 ,  G11C11/15 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C2211/5615 ,  G11C2211/562 ,  G11C2211/5633 ,  H01L27/222 ,  H01L27/228 ,  H01L43/08

Abstract: A multi-free layer magnetic tunnel junction (MTJ) cell includes a bottom electrode layer, an antiferromagnetic layer on the bottom electrode layer, a fixed magnetization layer on the antiferromagnetic layer and a barrier layer on the fixed magnetization layer. A first free magnetization layer is on a first area of the barrier layer, and a capping layer is on the first free magnetization layer. A free magnetization layer is on a second area of the barrier layer, laterally displaced from the first area, and a capping layer is on the second free magnetization layer. Optionally current switches establish a read current path including the first free magnetization layer concurrent with not establishing a read current path including the second free magnetization layer. Optionally current switches establishing a read current path including the first and second free magnetization layer.

Abstract translation: 多自由层磁隧道结（MTJ）单元包括底部电极层，底部电极层上的反铁磁层，反铁磁层上的固定磁化层和固定磁化层上的阻挡层。 第一自由磁化层位于阻挡层的第一区域上，盖层位于第一自由磁化层上。 自由磁化层位于阻挡层的第二区域上，与第一区域横向偏移，并且封盖层位于第二自由磁化层上。 可选地，电流开关在未建立包括第二自由磁化层的读取电流路径的同时建立包括第一自由磁化层的读取电流路径。 可选地，电流开关建立包括第一和第二自由磁化层的读取电流路径。

公开(公告)号：WO2012018918A3

公开(公告)日：2012-05-31

申请号：PCT/US2011046429

申请日：2011-08-03

Applicant: QUALCOMM INC ,  RAO HARI M ,  KIM JUNG PILL ,  KANG SEUNG H ,  ZHU XIAOCHUN ,  KIM TAE HYUN ,  LEE KANGHO ,  LI XIA ,  HSU WAH NAM ,  HAO WUYANG ,  SUH JUNGWON ,  YU NICHOLAS K ,  NOWAK MATTHEW MICHAEL ,  MILLENDORF STEVEN M ,  ASHKENAZI ASAF

Inventor： RAO HARI M ,  KIM JUNG PILL ,  KANG SEUNG H ,  ZHU XIAOCHUN ,  KIM TAE HYUN ,  LEE KANGHO ,  LI XIA ,  HSU WAH NAM ,  HAO WUYANG ,  SUH JUNGWON ,  YU NICHOLAS K ,  NOWAK MATTHEW MICHAEL ,  MILLENDORF STEVEN M ,  ASHKENAZI ASAF

IPC: G11C17/16 ,  G11C11/16 ,  G11C17/02

CPC classification number: G11C11/16 ,  G11C11/14 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C17/02 ,  G11C17/16 ,  G11C29/027

Abstract: A method of generating a non - reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device (102) includes a bitcell having a first MTJ (106) and a second MTJ (108) and programming circitry (104) configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell.

Abstract translation: 在具有第一磁性隧道结（MTJ）和第二MTJ的位单元处产生不可逆状态的方法包括将编程电压施加到位单元的第一MTJ，而不将编程电压施加到位单元的第二MTJ。 存储器设备（102）包括具有第一MTJ（106）和第二MTJ（108）和编程环绕（104）的比特单元，其被配置为通过将程序信号施加到所选择的一个中的所选择的一个来生成位单元的不可逆状态 第一个MTJ和该位单元的第二个MTJ。

公开(公告)号：WO2011088375A3

公开(公告)日：2011-09-22

申请号：PCT/US2011021376

申请日：2011-01-14

Applicant: QUALCOMM INC ,  CHEN WEI-CHUAN ,  KANG SEUNG H ,  ZHU XIAOCHUN

Inventor： CHEN WEI-CHUAN ,  KANG SEUNG H ,  ZHU XIAOCHUN

IPC: H01L27/22 ,  B82Y25/00 ,  G11C11/16 ,  H01F10/32 ,  H01L43/08

CPC classification number: B82Y25/00 ,  B82Y10/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/32 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) storage element (300) and method of forming the MTJ are disclosed. The magnetic tunnel junction (MTJ) storage element includes a pinned layer (206, 210), a barrier layer (212), a free layer (214) and a composite hardmask or top electrode (304, 306). The composite hardmask / top electrode architecture is configured to provide a non -uniform current path through the MTJ storage element and is formed from electrodes having different resistance characteristics coupled in parallel. An optional tuning layer (302) interposed between the free layer and the top electrode helps to reduce the damping constant of the free layer.

Abstract translation: 公开了磁性隧道结（MTJ）存储元件（300）和形成MTJ的方法。 磁性隧道结（MTJ）存储元件包括被钉扎层（206,210），阻挡层（212），自由层（214）和复合硬掩模或顶部电极（304,306）。 复合硬掩模/顶电极结构被配置为提供穿过MTJ存储元件的不均匀的电流路径，并且由具有并联耦合的不同电阻特性的电极形成。 插入在自由层和顶部电极之间的可选的调谐层（302）有助于减小自由层的阻尼常数。

公开(公告)号：WO2011072058A2

公开(公告)日：2011-06-16

申请号：PCT/US2010059541

申请日：2010-12-08

Applicant: QUALCOMM INC ,  ZHU XIAOCHUN ,  KANG SEUNG H ,  LI XIA ,  LEE KANGHO

Inventor： ZHU XIAOCHUN ,  KANG SEUNG H ,  LI XIA ,  LEE KANGHO

IPC: H01L43/08

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A system and method of manufacturing and using a magnetic tunnel junction device is disclosed. In a particular embodiment, a magnetic tunnel junction device includes a first free layer and second free layer. The magnetic tunnel junction also includes a spin torque enhancement layer. The magnetic tunnel junction device further includes a spacer layer between the first and second free layers that includes a material and has a thickness that substantially inhibits exchange coupling between the first and second free layers. The first and second free layers are magneto-statically coupled.

Abstract translation: 公开了制造和使用磁性隧道结装置的系统和方法。 在特定实施例中，磁性隧道结装置包括第一自由层和第二自由层。 磁隧道结还包括自旋转矩增强层。 磁性隧道结器件还包括位于第一和第二自由层之间的间隔层，其包括材料并且具有基本上抑制第一和第二自由层之间的交换耦合的厚度。 第一和第二自由层是磁静态耦合的。

公开(公告)号：WO2013071254A3

公开(公告)日：2013-11-14

申请号：PCT/US2012064703

申请日：2012-11-12

Applicant: QUALCOMM INC

Inventor： ZHU XIAOCHUN ,  LI SEAN ,  WU WENQING ,  KIM JUNG PILL ,  KANG SEUNG H

IPC: G11C11/16 ,  G11C5/14

CPC classification number: G11C11/16 ,  G11C5/147 ,  G11C11/1673

Abstract: A method of establishing a reference level includes providing first and second non-overlapping paths from a first node to a second node, providing first and second reference magnetic random access memory (MRAM) elements in the first path, providing third and fourth reference MRAM elements in the second path, measuring a first value indicative of a resistance between the first node and the second node, and setting the reference level based at least in part on the measured value. Also an associated reference circuit.

Abstract translation: 建立参考电平的方法包括提供从第一节点到第二节点的第一和第二非重叠路径，在第一路径中提供第一和第二参考磁随机存取存储器（MRAM）元件，提供第三和第四参考MRAM元件 在所述第二路径中，测量指示所述第一节点和所述第二节点之间的电阻的第一值，并且至少部分地基于所述测量值来设置所述参考电平。 还有一个相关的参考电路。