公开(公告)号：WO2009029520A1

公开(公告)日：2009-03-05

申请号：PCT/US2008/074016

申请日：2008-08-22

Applicant: RAMBUS INC. ,  LAMBRECHT, Frank ,  FRANCA-NETO, Luiz, M.

Inventor： LAMBRECHT, Frank ,  FRANCA-NETO, Luiz, M.

IPC: H01Q1/24 ,  H01Q21/00

CPC classification number: H01Q1/243 ,  H01Q21/0006 ,  H05K1/147

Abstract: An antenna array can be mounted on a flexible substrate and connected by a flexible interconnect to an integrated circuit such as a radio frequency front end. The antenna array can be mounted in a device housing that includes radio frequency interference (RFI) shielding. The antenna array is aligned with and next to an area of the housing that is not shielded against RFI.

Abstract translation: 天线阵列可以安装在柔性基板上，并通过柔性互连连接到诸如射频前端的集成电路。 天线阵列可以安装在包括射频干扰（RFI）屏蔽的设备外壳中。 天线阵列与壳体的不被屏蔽RFI的区域对准并且紧邻RFI的区域。

公开(公告)号：WO2008097997A1

公开(公告)日：2008-08-14

申请号：PCT/US2008/053082

申请日：2008-02-05

Applicant: RAMBUS INC. ,  LAMBRECHT, Frank

Inventor： LAMBRECHT, Frank

IPC: H01L25/10

CPC classification number: H01L23/48 ,  G11C5/025 ,  G11C5/04 ,  G11C7/1057 ,  G11C7/1084 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/181 ,  H05K2201/097 ,  H05K2201/10159 ,  H05K2203/1572 ,  Y02P70/611 ,  H01L2924/00

Abstract: The semiconductor module includes a plurality of memory die on a first side of a substrate and a plurality of buffer die on a second side of the substrate. Each of the memory die is disposed opposite and electrically coupled to one of the buffer die.

Abstract translation: 半导体模块包括在衬底的第一侧上的多个存储器管芯和在衬底的第二侧上的多个缓冲管芯。 每个存储器管芯相对设置并电耦合到缓冲管芯之一。

公开(公告)号：WO2005089407A2

公开(公告)日：2005-09-29

申请号：PCT/US2005/008830

申请日：2005-03-16

Applicant: RAMBUS, INC. ,  BEST, Scott, C. ,  ABHYANKAR, Abhijit, M. ,  CHANG, Kun-Yung ,  LAMBRECHT, Frank

Inventor： BEST, Scott, C. ,  ABHYANKAR, Abhijit, M. ,  CHANG, Kun-Yung ,  LAMBRECHT, Frank

IPC: G06F1/04 ,  H04L7/00 ,  H04L7/10 ,  H04L25/14

CPC classification number: G06F1/08 ,  G06F1/12 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14

Abstract: A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

Abstract translation: 通信信道包括具有耦合到正常信号源的发射机的第一分量和具有耦合到正常信号目的地的接收机的第二分量。 通信链路耦合第一和第二组件。 校准逻辑提供了设置通信信道参数的操作值，例如通过在链路初始化时执行穷举校准序列。 包括监视功能的跟踪电路通过监视具有与通信信道中的漂移相关的特征的反馈信号来跟踪参数中的漂移，并且更新或指示更新参数的操作值的需要 响应监控功能。

公开(公告)号：WO2004109702A1

公开(公告)日：2004-12-16

申请号：PCT/US2004/018226

申请日：2004-06-03

Applicant: RAMBUS INC. ,  BEST, Scott, C. ,  LAMBRECHT, Frank

Inventor： BEST, Scott, C. ,  LAMBRECHT, Frank

IPC: G11C7/22

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/22 ,  Y02D10/14

Abstract: Disclosed is a circuit for generating a clock signal to driver a plurality of memory components in a memory subsystern. The clock driver circuit comprises a clock generator for transmitting a clock signal to drive the plurality of memory components, a memory controller for controlling the plurality of memory components, and an adjustable impedance circuit residing within said memory controller such that the adjustable impedance circuit is programmable in accordance with a control input generated by the memory controller. The clock generator is configured to generate a clock signal with a voltage swing controlled by the impedance of the adjustable impedance circuit.

Abstract translation: 公开了一种用于产生时钟信号以驱动存储器子体中的多个存储器组件的电路。 时钟驱动器电路包括用于传输时钟信号以驱动多个存储器组件的时钟发生器，用于控制多个存储器组件的存储器控​​制器和驻留在所述存储器控制器内的可调阻抗电路，使得可调阻抗电路是可编程的 根据存储器控制器产生的控制输入。 时钟发生器被配置为产生具有由可调阻抗电路的阻抗控制的电压摆幅的时钟信号。

公开(公告)号：WO2009029335A1

公开(公告)日：2009-03-05

申请号：PCT/US2008/068822

申请日：2008-06-30

Applicant: RAMBUS INC. ,  KOLLIPARA, Ravindranath ,  YUAN, Xingchao ,  LAMBRECHT, Frank ,  LI, Ming ,  PEREGO, Richard E. ,  LIN, Qi ,  NGUYEN, David ,  OH, Kyung Suk

Inventor： KOLLIPARA, Ravindranath ,  YUAN, Xingchao ,  LAMBRECHT, Frank ,  LI, Ming ,  PEREGO, Richard E. ,  LIN, Qi ,  NGUYEN, David ,  OH, Kyung Suk

IPC: G06F13/16 ,  H01L25/10 ,  H05K1/00

CPC classification number: G06F13/1668 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0237 ,  H05K1/0295 ,  H05K1/14 ,  H05K1/141 ,  H05K1/147 ,  H05K3/222 ,  H05K2201/044 ,  H05K2201/09954 ,  H05K2201/10159 ,  H05K2201/10356

Abstract: The disclosure relates to a detachable signalling interconnect apparatus that provides connectivity between two or more components of a memory system in conjunction with different modes of operation of the components. The memory system comprises: a first socket to receive a first memory module; a second socket to receive a second memory module; a detachable signal-interconnect; and a memory controller coupled to the detachable signal-interconnect and configured to define a first mode of operation and a second mode of operation, wherein in the first mode of operation the detachable signal-interconnect is to couple the memory- controller to the first memory module and in the second mode of operation the detachable signal-interconnect is to couple the memory controller to the first memory module and the second memory module.

Abstract translation: 本公开涉及一种可拆卸信令互连装置，其提供存储器系统的两个或更多个组件与组件的不同操作模式之间的连接。 存储器系统包括：第一插座，用于接收第一存储器模块; 用于接收第二存储器模块的第二插座; 可拆卸的信号互连; 以及存储器控制器，其耦合到所述可拆卸信号互连并且被配置为限定第一操作模式和第二操作模式，其中在所述第一操作模式中，所述可拆卸信号互连将所述存储器控制器耦合到所述第一存储器 模块，并且在第二操作模式中，可拆卸信号互连将存储器控制器耦合到第一存储器模块和第二存储器模块。

公开(公告)号：WO2009151715A2

公开(公告)日：2009-12-17

申请号：PCT/US2009/038085

申请日：2009-03-24

Applicant: RAMBUS INC. ,  LEE, Fred S. ,  LAMBRECHT, Frank

Inventor： LEE, Fred S. ,  LAMBRECHT, Frank

IPC: G01D5/14

CPC classification number: G01D5/145 ,  G06F3/014

Abstract: Angular displacement of a flexible substrate is determined based on an electrical change of a mm-wave circuit associated with the flexible substrate. This electrical change may relate to, for example, one or more of a phase shift, an amplitude shift, a frequency shift, or a pulse shift. In some implementations the flexible substrate may include conductors on multiple layers whereby an angular displacement of the flexible substrate causes a relative displacement between conductors of different layers, thereby inducing the electrical change of the mm-wave circuit.

Abstract translation: 基于与柔性基板相关联的mm波形电路的电变化来确定柔性基板的角位移。 该电变化可以涉及例如相移，幅度偏移，频移或脉冲偏移中的一个或多个。 在一些实施方案中，柔性基板可以包括多层上的导体，由此柔性基板的角位移导致不同层的导体之间的相对位移，从而引起mm波电路的电变化。