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1.发明申请
公开(公告)号：WO2014070534A2
公开(公告)日：2014-05-08
申请号：PCT/US2013/066266
申请日：2013-10-23
申请人： RAYTHEON COMPANY
IPC分类号： H01L23/48 , H01L21/56 , H01L23/544
CPC分类号： B81B7/0041 , B81B7/007 , B81C1/00269 , B81C2203/019 , H01L23/053 , H01L24/27 , H01L24/29 , H01L24/83 , H01L2224/27444 , H01L2224/27462 , H01L2224/27464 , H01L2224/29011 , H01L2224/291 , H01L2224/83001 , H01L2224/83007 , H01L2224/83139 , H01L2224/8314 , H01L2224/83141 , H01L2224/83192 , H01L2924/1461 , H01L2924/163 , H01L2924/00014 , H01L2924/014
摘要： A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.
摘要翻译： 一种形成晶片级封装电路器件的方法包括形成器件晶片，器件晶片包括残留在器件晶片的衬底的第一区域中的第一组一个或多个材料层; 以及形成被配置为附接到所述器件晶片的盖晶片，所述盖晶片包括留在所述盖晶片的衬底的第二区域中的第二组一个或多个材料层; 其中一个或多个材料层的所述第一和第二组的组合厚度在所述器件晶片和所述盖晶片接合时限定了整合的接合间隙控制结构。
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公开(公告)号：WO2021167662A1
公开(公告)日：2021-08-26
申请号：PCT/US2020/060845
申请日：2020-11-17
申请人： RAYTHEON COMPANY
摘要： Imaging and ALPD device and method of use is disclosed. A detector (104) generates an electrical signal in response to receiving an optical signal (115), wherein a frequency of the electrical signal is indicative of a frequency of the optical signal. A first detection/readout circuit (ROIC1) is sensitive to a first frequency range, and a second detection/readout circuit (ROIC2) is sensitive to a second frequency range. The first detection/readout circuit allows the electrical signal to pass from the first detection/readout circuit to the second detection/readout circuit.
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公开(公告)号：WO2016209339A1
公开(公告)日：2016-12-29
申请号：PCT/US2016/028338
申请日：2016-04-20
申请人： RAYTHEON COMPANY
CPC分类号： B81B7/0058 , B81B7/0041 , B81B2201/0207 , B81B2201/04 , B81C1/00269 , B81C1/00317 , B81C2203/0109 , B81C2203/0118 , B81C2203/0145 , B81C2203/019
摘要： A microelectromechanical systems (MEMS) package includes a substrate extending between a first pair of outer edges to define a length and a second pair of outer edges to define a width. A seal ring assembly is disposed on the substrate and includes at least one seal ring creating a first boundary point adjacent to at least one MEMS device and a second boundary point adjacent at least one of the outer edges. The package further includes a window lid on the seal ring assembly to define a seal gap containing the at least one MEMS device. The seal ring assembly anchors the window lid to the substrate at the second boundary point such that deflection of the window lid into the seal gap is reduced.
摘要翻译： 微机电系统（MEMS）封装包括在第一对外边缘之间延伸以限定长度的基板和限定宽度的第二对外边缘。 密封环组件设置在基板上，并且包括至少一个密封环，其形成与至少一个MEMS装置相邻的第一边界点和邻近至少一个外边缘的第二边界点。 封装还包括在密封环组件上的窗口盖，以限定包含至少一个MEMS器件的密封间隙。 密封圈组件在第二边界点将窗口盖固定到基底，使得窗口盖进入密封间隙的偏转减小。
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公开(公告)号：WO2013192132A1
公开(公告)日：2013-12-27
申请号：PCT/US2013/046231
申请日：2013-06-18
申请人： RAYTHEON COMPANY
IPC分类号： H01L27/146
CPC分类号： G01S13/89 , G01S2007/028 , H01L21/568 , H01L24/19 , H01L24/96 , H01L2223/6655 , H01L2223/6677 , H01L2224/04105 , H01L2224/24137 , H01L2224/32245 , H01L2224/73267 , H01Q1/2283 , H01Q21/0006
摘要： A receiver chip for use in an imaging system includes a plurality of receiver dies, each of the receiver dies comprising one or more receiver circuits; a die interconnection layer located on top of the plurality of receiver dies; a quarter wave dielectric layer located on top of the die interconnection layer; and a plurality of antennae located on the quarter wave dielectric layer, each of the plurality of antennae corresponding to a respective receiver circuit, wherein the plurality of antennae are connected to the one or more receiver circuits through the quarter wave dielectric layer and the die interconnection layer by respective vias, such that a distance between a topmost layer of the die interconnection layer and the plurality of antennae is determined by a thickness of the quarter wave dielectric layer.
摘要翻译： 用于成像系统的接收器芯片包括多个接收器管芯，每个接收器管芯包括一个或多个接收器电路; 位于所述多个接收器管芯的顶部上的管芯互连层; 位于芯片互连层顶部的四分之一波长介电层; 以及位于所述四分之一波长介电层上的多个天线，所述多个天线中的每一个对应于相应的接收器电路，其中所述多个天线通过所述四分之一波长介电层连接到所述一个或多个接收器电路，并且所述管芯互连 使得芯片互连层的最上层与多个天线之间的距离由四分之一波长介电层的厚度确定。
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公开(公告)号：WO2005038909A3
公开(公告)日：2005-04-28
申请号：PCT/US2004/034302
申请日：2004-10-16
申请人： RAYTHEON COMPANY
IPC分类号： H01L31/0203
摘要： A radiation detector (10) has a base (30), a frame (48), a window (46), and solder layers (50,52) formed from a solder pre-form to define a vacuum chamber (56). Feedthroughs (18,40,44) penetrate the base (30) for electrical connection to internal components. A method for sealing the detector aligns a lower detector assembly (62), the frame (48), the window (46), and the solder pre-forms (58,60) in a non-sealed relation within a processing chamber (80,94). High temperature and low pressure is imposed, and the getter (42) is activated by resistive heating imposed by current leads. The window (46), frame (48), and lower detector assembly (62) are then pressed together and sealed by the liquefied solder pre-forms (58,60). The method eliminates the need for a seal port, combines several steps within the processing chamber, and eliminates certain prior art cleaning steps.
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