公开(公告)号：WO2008057179A2

公开(公告)日：2008-05-15

申请号：PCT/US2007/022198

申请日：2007-10-18

Applicant: RAYTHEON COMPANY ,  TABATABAIE, Kamal ,  HALLOCK, Robert, B.

Inventor： TABATABAIE, Kamal ,  HALLOCK, Robert, B.

IPC: H01L21/335 ,  H01L21/285

CPC classification number: H01L21/28587 ,  H01L29/66462

Abstract: A semiconductor structure having a recess and a dielectric film is disposed on and in contract with the semiconductor. The dielectric film has an aperture therein. Portions of the dielectric film are disposed adjacent to the aperture and overhang underlying portions of the recess. An electric contact has first portions thereof disposed on said adjacent portions of the dielectric film, second portions disposed on said underlying portions of the recess, with portions of the dielectric film being disposed between said first portion of the electric contact and the second portions of the electric contact, and third portions of the electric contact being disposed on and in contact with a bottom portion of the recess in the semiconductor structure. The electric contact is formed by atomic layer deposition of an electrically conductive material over the dielectric film and through the aperture in such dielectric film.

Abstract translation: 具有凹部和电介质膜的半导体结构设置在半导体上并与其接合。 电介质膜具有孔。 电介质膜的一部分设置成与凹部的孔和悬垂下部相邻。 电触头的第一部分设置在电介质膜的相邻部分上，第二部分设置在凹槽的下面部分上，电介质膜的部分设置在电触点的第一部分和第二部分之间 电接触，并且电接触件的第三部分设置在半导体结构中的凹部的底部上并与其接触。 电接触通过在电介质膜上并通过这种电介质膜中的孔的原子层沉积导电材料形成。

公开(公告)号：WO2010085458A1

公开(公告)日：2010-07-29

申请号：PCT/US2010/021443

申请日：2010-01-20

Applicant: RAYTHEON COMPANY ,  TABATABAIE, Kamal ,  DAVIS, Michael, S. ,  LAROCHE, Jeffrey, R. ,  KAPER, Valery, S. ,  BETTENCOURT, John, P.

Inventor： TABATABAIE, Kamal ,  DAVIS, Michael, S. ,  LAROCHE, Jeffrey, R. ,  KAPER, Valery, S. ,  BETTENCOURT, John, P.

IPC: H01L21/8258 ,  H01L23/485 ,  H01L27/06 ,  H01L27/092

CPC classification number: H01L21/8258 ,  H01L23/485 ,  H01L23/53238 ,  H01L27/0605 ,  H01L27/0623 ,  H01L27/0922 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure having a substrate (12) a seed layer (13) over the substrate; a silicon layer (22) disposed on the seed layer; a transistor device (27) in the silicon layer; a III-V device disposed on the seed layer; and a plurality of electrical contacts, each one of the electrical contacts having a layer (32) of TiN or TaN and a layer (34) of copper or aluminum on the layer of TaN or TiN, one of the electrical contacts being electrically connected to the transistor (27) and another one of the electrical contacts being electrically connected to the III-V device.

Abstract translation: 一种半导体结构，在衬底上具有衬底（12）种子层（13）; 设置在种子层上的硅层（22）; 硅层中的晶体管器件（27）; 设置在种子层上的III-V装置; 和多个电触点，每个电触点具有TiN或TaN的层（32）和TaN或TiN层上的铜或铝层（34），其中一个电触点电连接到 晶体管（27）和另一个电触点电连接到III-V器件。

公开(公告)号：WO2010085459A1

公开(公告)日：2010-07-29

申请号：PCT/US2010/021444

申请日：2010-01-20

Applicant: RAYTHEON COMPANY ,  TABATABAIE, Kamal ,  LAROCHE, Jeffrey, R. ,  KAPER, Valery, S. ,  BETTENCOURT, John, P. ,  IP, Kelly, P.

Inventor： TABATABAIE, Kamal ,  LAROCHE, Jeffrey, R. ,  KAPER, Valery, S. ,  BETTENCOURT, John, P. ,  IP, Kelly, P.

IPC: H01S5/026 ,  H01S5/183 ,  H01L21/331

CPC classification number: H01S5/0261 ,  H01L27/0617 ,  H01S5/021 ,  H01S5/02248 ,  H01S5/0262 ,  H01S5/183 ,  H01S5/2214 ,  H01S2301/173

Abstract: A semiconductor structure, comprising: a substrate (12); a seed layer (16) over an upper surface of the substrate (12); a semiconductor layer (20) disposed over the seed layer (16); a transistor device (22, 24) in the semiconductor layer (20); wherein the substrate (12) has an aperture (42) therein, such aperture (42) extending from a bottom surface of the substrate (12) and terminating on a bottom surface of the seed layer (16); and an opto-electric structure (44) disposed on the bottom surface of the seed layer (16).

Abstract translation: 一种半导体结构，包括：衬底（12）; 在所述基板（12）的上表面上方的种子层（16）; 设置在种子层（16）上的半导体层（20）; 半导体层（20）中的晶体管器件（22,24）; 其中所述基底（12）中具有孔（42），所述孔（42）从所述基底（12）的底表面延伸并终止于所述籽晶层（16）的底表面上。 以及设置在种子层（16）的底表面上的光电结构（44）。

公开(公告)号：WO2014011332A1

公开(公告)日：2014-01-16

申请号：PCT/US2013/044254

申请日：2013-06-05

Applicant: RAYTHEON COMPANY

Inventor： TABATABAIE, Kamal ,  HOKE, William, E. ,  CHUMBES, Eduardo, M. ,  MCCARTHY, Kevin

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/66462 ,  H01L29/0657 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/7787 ,  H01L29/7789

Abstract: A semiconductor structure having mesa structure comprising: a lower semiconductor layer; an upper semiconductor layer having a higher band gap than, and in direct contact with, the lower semiconductor layer to form a two-dimension electron gas (2DEG) region between the upper semiconductor layer. The 2DEG region has outer edges terminating at sidewalls of the mesa. An additional electron donor layer has a band gap higher than the band gap of the lower layer disposed on sidewall portions of the mesa structure and on the region of the 2DEG region terminating at sidewalls of the mesa. An ohmic contact material is disposed on the electron donor layer. A sideway HEMT is formed with the electron donor layer, the 2DEG region and the ohmic contact material increasing the concentration of electrons (i.e., lowering ohmic contact resistance) along the contact between the lower semiconductor layer and the electron donor layer.

Abstract translation: 一种具有台面结构的半导体结构，包括：下半导体层; 上半导体层具有比下半导体层更高的带隙并且与下半导体层直接接触以在上半导体层之间形成二维电子气（2DEG）区。 2DEG区域具有终止于台面侧壁的外边缘。 另外的电子供体层的带隙高于设置在台面结构的侧壁部分上的下层的带隙，并且终止于台面的侧壁处的2DEG区域的区域。 欧姆接触材料设置在电子供体层上。 侧电HEMT与电子供体层，2DEG区和欧姆接触材料形成，沿着下半导体层和电子供体层之间的接触增加电子的浓度（即降低欧姆接触电阻）。

公开(公告)号：WO2015050633A1

公开(公告)日：2015-04-09

申请号：PCT/US2014/050642

申请日：2014-08-12

Applicant: RAYTHEON COMPANY

Inventor： LILES, Barry, J. ,  TABATABAIE, Kamal ,  ROSE, Frederick, A. ,  MACDONALD, Christopher, J. ,  RYAN, Paul, M. ,  SMITH, Kurt, V. ,  SMITH, Irl, W.

IPC: H01L29/417 ,  H01L23/482 ,  H01L29/812

CPC classification number: H01L23/53238 ,  H01L23/4821 ,  H01L29/41758 ,  H01L29/8124 ,  H01L2924/13063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure having first and second electrical conductors disposed on a surface of the structure and a bridging conductor connected between the first electrical conductor and the second electrical conductor with portions disposed over the surface of the structure. The bridging conductor includes a plurality of stacked, multi-metal layers, each one of the multi -metal layers having: an electrically conductive layer; and a pair of barrier metal layers, the electrically conductive layer being disposed between and in direct contact with the pair of barrier metal layers.

Abstract translation: 一种结构，其具有布置在该结构的表面上的第一和第二电导体以及连接在第一电导体和第二电导体之间的桥接导体，其中部分设置在该结构的表面上。 桥接导体包括多个堆叠的多金属层，每个多金属层具有：导电层; 以及一对势垒金属层，所述导电层设置在所述一对势垒金属层之间并与所述一对势垒金属层直接接触。

公开(公告)号：WO2013126153A1

公开(公告)日：2013-08-29

申请号：PCT/US2013/020611

申请日：2013-01-08

Applicant: RAYTHEON COMPANY

Inventor： DUVAL, Paul, J. ,  TABATABAIE, Kamal ,  DAVIS, William, J.

IPC: H01L23/544 ,  G03F7/20 ,  G03F9/00

CPC classification number: H01L21/71 ,  G03F9/7076 ,  G03F9/708 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Forming an alignment mark on a semiconductor structure using an optical lithography to form a metal alignment mark on a substrate of the structure, using the formed metal alignment mark to form a first feature of a semiconductor device being formed on the substrate using optical lithography, and using the formed metal alignment mark to form a second, different feature for the semiconductor using electron beam lithography. In one embodiment, the first feature is an ohmic contact, the second feature is a Schottky contact, the metal alignment mark is a refractory metal or a refractory metal compound having an atomic weight greater than 60 such as TaN and the semiconductor device is a GaN semiconductor device. A semiconductor structure having a metal alignment mark on a zero layer of the structure, the metal alignment mark is a TaN and the semiconductor is GaN.

Abstract translation: 使用光刻法在半导体结构上形成对准标记，以在结构的基板上形成金属对准标记，使用所形成的金属对准标记，以形成利用光刻法形成在基板上的半导体器件的第一特征，以及 使用形成的金属对准标记来形成使用电子束光刻的半导体的第二不同特征。 在一个实施例中，第一特征是欧姆接触，第二特征是肖特基接触，金属对准标记是原子量大于60的难熔金属或难熔金属化合物，例如TaN，并且半导体器件是GaN 半导体器件。 在结构的零层上具有金属对准标记的半导体结构，金属对准标记为TaN，半导体为GaN。

公开(公告)号：WO2008057184A2

公开(公告)日：2008-05-15

申请号：PCT/US2007/022217

申请日：2007-10-18

Applicant: RAYTHEON COMPANY ,  TABATABAIE, Kamal

Inventor： TABATABAIE, Kamal

CPC classification number: H01L29/402 ,  H01L29/1608 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/812

Abstract: A method for forming a transistor device having a field plate includes forming a structure having a source, a drain, and a Tee gate. A photo-resist layer is formed on the structure with an opening therein only the one of two distal ends of the Tee gate. A metal is deposited over the photo-resist layer with portions of the metal being disposed on the photo-resist layer and with other portions of the metal passing through the opening onto the exposed portions of the dielectric layer and with distal end of the top of the Tee gate preventing such metal from being deposited onto portions of the dielectric layer disposed under it. The photo-resist layer is removed along with the portions of the metal deposited thereon while leaving portions of the metal from regions of the dielectric layer exposed by the opening to form the field gate.

Abstract translation: 用于形成具有场板的晶体管器件的方法包括形成具有源极，漏极和T形栅极的结构。 在其上具有开口的结构上形成光刻胶层，仅暴露三通门的两个远端中的一个。 金属沉积在光致抗蚀剂层上，其中金属的一部分设置在光致抗蚀剂层上，并且金属的其它部分通过开口穿过介电层的暴露部分，并且顶部的顶端 T形门防止这种金属沉积在设置在其下的介电层的部分上。 光致抗蚀剂层与沉积在其上的金属的一部分一起被去除，同时从由开口暴露的电介质层的区域留出部分金属以形成场栅。