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1.
公开(公告)号:WO2020251626A1
公开(公告)日:2020-12-17
申请号:PCT/US2019/068868
申请日:2019-12-30
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: WU, Chen , RABKIN, Peter , HIGASHITANI, Masaaki
IPC: H01L23/538 , H01L23/522 , H01L25/065 , H01L21/822 , H01L21/8229
Abstract: A method of forming a bonded assembly includes providing a first semiconductor die containing a first substrate, first semiconductor devices, first dielectric material layers overlying the first semiconductor devices, and first metal interconnect structures, providing a second semiconductor die containing a second substrate, second semiconductor devices, second dielectric material layers overlying the second semiconductor devices, and second metal interconnect structures, depositing a manganese layer on a top surface of the first dielectric material layers, disposing the second semiconductor die on the manganese layer such that a surface of the second dielectric material layers contacts the manganese layer, and performing a bonding anneal to bond the first semiconductor die to the second semiconductor die and to convert the manganese layer into a manganese-containing oxide layer, such that the manganese-containing oxide layer is bonded to the first dielectric material layers and the second dielectric material layers.
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2.
公开(公告)号:WO2021145916A1
公开(公告)日:2021-07-22
申请号:PCT/US2020/035612
申请日:2020-06-01
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: WU, Chen , RABKIN, Peter , HIGASHITANI, Masaaki
IPC: H05K3/04 , H01L29/40 , H05K3/10 , H01L23/532 , H01L21/768 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03614 , H01L2224/03616 , H01L2224/03622 , H01L2224/05557 , H01L2224/05567 , H01L2224/0557 , H01L2224/05583 , H01L2224/05647 , H01L2224/08147 , H01L2224/80001 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/89 , H01L25/18 , H01L25/50 , H01L27/11526 , H01L27/11556 , H01L2924/1431 , H01L2924/14511
Abstract: A semiconductor die includes a first pad-level dielectric layer embedding first bonding pads and located over a first substrate. Each of the first bonding pads is located within a respective pad cavity in the first pad-level dielectric layer. Each of the first bonding pads includes a first metallic liner containing a first metallic liner material and contacting a sidewall of the respective pad cavity, a first metallic fill material portion embedded in the first metallic liner, and a metallic electromigration barrier layer contacting the first metallic fill material portion and adjoined to the first metallic liner.
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3.
公开(公告)号:WO2021107970A1
公开(公告)日:2021-06-03
申请号:PCT/US2020/023254
申请日:2020-03-18
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: WU, Chen , RABKIN, Peter , CHEN, Yangyin , HIGASHITANI, Masaaki
IPC: H01L25/065 , H01L23/31 , H01L23/00 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582
Abstract: A bonded assembly includes a first die containing first bonding pads having sidewalls that are laterally bonded to sidewalls of second bonding pads of a second die.
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4.
公开(公告)号:WO2021096552A1
公开(公告)日:2021-05-20
申请号:PCT/US2020/023163
申请日:2020-03-17
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: WU, Chen , RABKIN, Peter , CHEN, Yangyin , HIGASHITANI, Masaaki
Abstract: A bonded assembly and a method of forming a bonded assembly includes providing a first semiconductor die including a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, providing a second semiconductor die including a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices, forming a dielectric bonding pattern definition layer including bonding pattern definition openings therethrough over the second bonding pads, and bonding the second bonding pads to the first bonding pads, where the first metal pads expand through the bonding pattern definition openings and are bonded to a respective one of the second bonding pads.
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5.
公开(公告)号:WO2021177990A1
公开(公告)日:2021-09-10
申请号:PCT/US2020/037619
申请日:2020-06-12
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: WU, Chen , RABKIN, Peter , CHEN, Yangyin , HIGASHITANI, Masaaki
IPC: H01L21/768 , H01L21/02 , H01L23/495 , B23K26/36 , H01L27/11582 , H01L27/11556
Abstract: A method of forming a semiconductor structure includes forming first semiconductor devices over a first substrate, forming a first dielectric material layer over the first semiconductor devices, forming vertical recesses in the first dielectric material layer, such that each of the vertical recesses vertically extends from a topmost surface of the first dielectric material layer toward the first substrate, forming silicon nitride material portions in each of the vertical recesses; and locally irradiating a second subset of the silicon nitride material portions with a laser beam. A first subset of the silicon nitride material portions that is not irradiated with the laser beam includes first silicon nitride material portions that apply tensile stress to respective surrounding material portions, and the second subset of the silicon nitride material portions that is irradiated with the laser beam includes second silicon nitride material portions that apply compressive stress to respective surrounding material portions.
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6.
公开(公告)号:WO2021107971A1
公开(公告)日:2021-06-03
申请号:PCT/US2020/023493
申请日:2020-03-19
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: WU, Chen , RABKIN, Peter , HIGASHITANI, Masaaki
IPC: H01L25/065 , H01L23/31 , H01L23/00 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582
Abstract: A first semiconductor die includes first bonding pads. The first bonding pads include proximal bonding pads embedded within a first bonding dielectric layer and distal bonding pads having at least part of the sidewall that overlies the first bonding dielectric layer. A second semiconductor die includes second bonding pads. The second bonding pads are bonded to the proximal bonding pads and the distal bonding pads. The proximal bonding pads are bonded to a respective one of a first subset of the second bonding pads at a respective horizontal bonding interface and the distal bonding pads are bonded to a respective one of a second subset of the second bonding pads at a respective vertical bonding interface at the same time. Dielectric isolation structures may vertically extend through the second bonding dielectric layer of the second semiconductor die and contact the first bonding dielectric layer.
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公开(公告)号:WO2021040809A1
公开(公告)日:2021-03-04
申请号:PCT/US2020/026106
申请日:2020-04-01
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: WU, Chen , RABKIN, Peter , CHEN, Yangyin , HIGASHITANI, Masaaki
IPC: H01L25/065 , H01L23/48 , H01L23/00 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L27/11524 , H01L27/11529 , H01L27/11556
Abstract: A semiconductor structure includes a first semiconductor die containing a recesses, and a second semiconductor die which is embedded in the recess in the first semiconductor die and is bonded to the first semiconductor die.
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8.
公开(公告)号:WO2021015827A1
公开(公告)日:2021-01-28
申请号:PCT/US2020/024138
申请日:2020-03-23
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: WU, Chen , RABKIN, Peter , CHEN, Yangyin , HIGASHITANI, Masaaki
IPC: H01L25/065 , H01L23/31 , H01L23/48 , H01L23/00 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582
Abstract: A bonded assembly includes a first semiconductor die including a first substrate, first semiconductor devices located on the first substrate, first dielectric material layers located on the first semiconductor devices and embedding first metal interconnect structures, and first through-substrate via structures extending through the first substrate and contacting a respective first metal interconnect structure. Each of the first through-substrate via structures laterally surrounds a respective core cavity that contains a void or a dielectric fill material portion. The bonded assembly includes a second semiconductor die attached to the first semiconductor die, and including a second substrate, second semiconductor devices located on the second substrate, second dielectric material layers located on the second semiconductor devices and embedding second metal interconnect structures, and bonding pad structures electrically connected to a respective one of the second metal interconnect structures and bonded to a respective first through-substrate via structure.
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