公开(公告)号：WO2021145916A1

公开(公告)日：2021-07-22

申请号：PCT/US2020/035612

申请日：2020-06-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： WU, Chen ,  RABKIN, Peter ,  HIGASHITANI, Masaaki

IPC: H05K3/04 ,  H01L29/40 ,  H05K3/10 ,  H01L23/532 ,  H01L21/768 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/03622 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/80001 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/89 ,  H01L25/18 ,  H01L25/50 ,  H01L27/11526 ,  H01L27/11556 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor die includes a first pad-level dielectric layer embedding first bonding pads and located over a first substrate. Each of the first bonding pads is located within a respective pad cavity in the first pad-level dielectric layer. Each of the first bonding pads includes a first metallic liner containing a first metallic liner material and contacting a sidewall of the respective pad cavity, a first metallic fill material portion embedded in the first metallic liner, and a metallic electromigration barrier layer contacting the first metallic fill material portion and adjoined to the first metallic liner.

公开(公告)号：WO2023272903A1

公开(公告)日：2023-01-05

申请号：PCT/CN2021/113329

申请日：2021-08-18

Applicant: 长鑫存储技术有限公司

Inventor： 庄凌艺

IPC: H01L23/482 ,  H01L23/528 ,  H01L21/768 ,  H01L2224/039 ,  H01L2224/05013 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05573 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/08147 ,  H01L2224/80895 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80

Abstract: 一种半导体结构，包括：第一衬底（11），所述第一衬底（11）的表面具有第一开口（11c）；第一键合结构（12），位于所述第一开口（11c）内；所述第一键合结构（12）包括第一金属层（121）和熔点小于所述第一金属层（121）的第二金属层（122），所述第一金属层（121）包括与所述第一开口（11c）的底面接触的第一表面（121a）以及与所述第一表面（121a）相对的第二表面（121b），所述第二表面（121b）上具有第一凹槽（121c），所述第一开口（11c）未被所述第一金属层（121）和所述第一凹槽（121c）占据的区域构成第二凹槽（11d），所述第二金属层（122）形成于所述第一凹槽（121c）和所述第二凹槽（11d）内，所述第二金属层（122）从所述第二凹槽（11d）暴露的表面构成所述第一键合结构（12）的键合用表面。

公开(公告)号：WO2022046482A2

公开(公告)日：2022-03-03

申请号：PCT/US2021/046455

申请日：2021-08-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KIRBY, Kyle K. ,  PAREKH, Kunal R.

IPC: H01L23/485 ,  H01L27/11573 ,  H01L21/60 ,  H01L21/683 ,  H01L21/50 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05647 ,  H01L2224/08058 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/13111 ,  H01L2224/80006 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/9202 ,  H01L2225/06541 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/11582

Abstract: Systems and methods for a semiconductor device having a front-end-of-line interconnect structure are provided. The semiconductor device may include a dielectric material having a backside formed on a front side of a semiconductor or silicon substrate material and a front side, and a conducting material on the front side of the dielectric material. The conducting material may have a line portion and an interconnect structure electrically coupled to the line portion and separated from the front side of the substrate material by the dielectric material. The interconnect structure has a backside defining a contact surface. The semiconductor device may further include a semiconductor die proximate the front side of the dielectric material, an insulating material encasing at least a portion of the semiconductor die, and an opening through which the active contact surface at the backside of the interconnect structure is exposed for electrical connection.