公开(公告)号：WO1995028005A2

公开(公告)日：1995-10-19

申请号：PCT/US1995004340

申请日：1995-04-07

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  SHU, William, K. ,  PAYNE, Robert, L.

IPC: H01L23/485

CPC classification number: H01L24/06 ,  H01L23/49541 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06153 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012

Abstract: A semiconductor die assembly of this invention includes a lead system in which the leads (16) are arranged in a radial pattern. That is, in a group of leads associated with a single side of a semiconductor die (10), leads which are furthest from the middle are most angled from the perpendicular. The semiconductor die includes an outer row of bond pads (12a) which are located proximate to the edge of the semiconductor die and an inner row of bond pads (12b), parallel to the first row and located toward the interior of the semiconductor die surface. In one embodiment, one of the rows of bond pads is regularly spaced, while the other row of bond pads is variably spaced. The bond pads of the variably spaced row are positioned such that a bond wire (18) which connects a bond pad of the inner row to its associated lead (16) will pass substantially medially between the centers of the two closest bond pads of the outer row.

Abstract translation: 本发明的半导体模具组件包括引线系统，其中引线（16）以径向图案布置。 也就是说，在与半导体管芯（10）的单侧相关联的一组引线中，距离中间最远的引线与垂直线最相似。 半导体管芯包括位于半导体管芯的边缘附近的外排接合焊盘（12a）和平行于第一排并位于半导体管芯表面的内部的内排接合焊盘（12b） 。 在一个实施例中，一排接合焊盘是规则间隔开的，而另一排接合焊盘是可变间隔开的。 可变间隔排的接合焊盘被定位成使得将内部列的接合焊盘连接到其相关联的引线（16）的接合线（18）将基本上中间地在外部的两个最接近的接合焊盘的中心之间 行。

公开(公告)号：WO1992008992A1

公开(公告)日：1992-05-29

申请号：PCT/US1991008372

申请日：1991-11-08

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  FONG, Carl, H. ,  SHU, William, K.

IPC: G01R31/00

CPC classification number: H01L24/05 ,  G01R1/04 ,  H01L22/34 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A novel test die is disclosed for use in conjunction with a semiconductor assembly machine or process. The test die includes a plurality of sets of bond pads having different bond pad pitches which permits testing of those pitches with use of a single die. Bond pads suitable for array bonding and having different bond pad pitches are also disclosed. Electrical connections are provided between bond pads and permit detection of open and short circuits or other circuit defects. A staggered arrangement of bond pads permits bond pads to be packed more densely on the die. A method for fabricating a wafer having a plurality of bond pads which form a repeating pattern is given. The patterned wafer may be cut to form a test die having bond pads which are positioned to provide bond pad pitches as required by a user.

Abstract translation: 公开了一种与半导体组装机器或工艺结合使用的新型测试模具。 测试模具包括具有不同键合间距的多组接合焊盘，其允许使用单个模具来测试这些间距。 还公开了适用于阵列结合并具有不同接合焊盘间距的焊盘。 在接合焊盘之间提供电连接，并允许检测开路和短路或其他电路缺陷。 接合焊盘的交错布置允许将焊盘更密集地封装在芯片上。 给出了一种制造具有形成重复图案的多个接合焊盘的晶片的方法。 图案化的晶片可以被切割以形成具有接合焊盘的测试管芯，所述接合焊盘被定位成提供用户所要求的接合焊盘间距。