公开(公告)号：WO2018024466A1

公开(公告)日：2018-02-08

申请号：PCT/EP2017/067840

申请日：2017-07-14

Applicant: ASML NETHERLANDS B.V.

Inventor： YPMA, Alexander ,  KOOPMAN, Adrianus, Cornelis, Matheus ,  MIDDLEBROOKS, Scott, Anderson

IPC: G03F7/20 ,  H01L21/66 ,  G06K9/62

CPC classification number: G03F7/70525 ,  G03F7/70508 ,  G03F7/70616 ,  G03F7/70625 ,  G03F7/70633 ,  G03F7/70641 ,  G05B19/41875 ,  G06K9/6296 ,  G06T7/001 ,  G06T2207/30148 ,  H01L22/20 ,  Y02P90/86

Abstract: A diagnostic system (242, 244, 236, 248) implements a network comprising two or more sub-domains (DOM-A, B, C). Each sub-domain comprises diagnostic information extracted by analysis of object data, the first object data representing one or more first parameters measured in relation to a first set of product units that have been subjected nominally to the same industrial process as one another. The network further comprises at least one probabilistic connection (622, 624, 626) from a first variable in a first diagnostic sub-domain to a second variable in a second diagnostic sub-domain. Part of the second diagnostic information is thereby being influenced probabilistically by knowledge within the first diagnostic information. Diagnostic information may comprise for example a spatial fingerprint observed in the object data, or inferred. The network may include connections within sub- domains. The network may form a directed acyclic graph, and used for Bayesian inference operations.

Abstract translation: 诊断系统（242,244,236,248）实现包括两个或更多个子域（DOM-A，B，C）的网络。 每个子域包括通过对象数据的分析而提取的诊断信息，第一对象数据表示关于第一组产品单位测量的一个或多个第一参数，第一组产品单位在名义上经历了彼此相同的工业过程。 网络还包括从第一诊断子域中的第一变量到第二诊断子域中的第二变量的至少一个概率连接（622,624,626）。 因此第二诊断信息的一部分由第一诊断信息内的知识概率性地受到影响。 诊断信息可以包括例如在对象数据中观察到的或推断的空间指纹。 网络可以包括子域内的连接。 网络可能形成有向无环图，并用于贝叶斯推理操作。

公开(公告)号：WO2017080735A1

公开(公告)日：2017-05-18

申请号：PCT/EP2016/074274

申请日：2016-10-11

Applicant: ASML NETHERLANDS B.V.

Inventor： DANILIN, Alexander, Alexandrovich

IPC: G03F7/20

CPC classification number: G03F7/70633 ,  G03F7/705 ,  G03F7/70508 ,  G03F7/70516

Abstract: Measurement data (902) is obtained for calibration fields that have been exposed by a lithographic apparatus using different field layouts and exposure sequences. The measurement data is classified in subset by scan direction, step direction, field size and other variables. The measurement data is indexed by a time value that varies through each exposure sequence. Time values within different exposure sequences can be related using a normalized time value (T) based on the beginning and end of each exposure sequence. An inter-field performance model (904) is calculated for each subset. An intra-field component (914) of a performance model is calculated with time as a third dimension. The time-indexed performance model is used to determine intra-field corrections for a variety of product exposures having product layouts and product exposure sequences different to the calibration fields, based on time and other a variables of the product layout and product exposure sequence. Time-based components can be inter-field and/or intra-field components.

Abstract translation: 测量数据（902）是针对已经由光刻设备使用不同的场布局和曝光序列曝光的校准场而获得的。 测量数据按照扫描方向，步进方向，字段大小和其他变量进行子集分类。 测量数据通过每个曝光顺序变化的时间值进行索引。 使用基于每个曝光序列的开始和结束的标准化时间值（T）可以将不同曝光序列内的时间值关联。 为每个子集计算场间性能模型（904）。 性能模型的场内组件（914）随着时间被计算为第三维度。 时间索引性能模型用于根据产品布局和产品暴露顺序的时间和其他变量来确定产品布局和产品暴露序列与校准领域不同的多种产品暴露的场内校正。 基于时间的组件可以是场内和/或场内组件。

公开(公告)号：WO2017076702A2

公开(公告)日：2017-05-11

申请号：PCT/EP2016/075701

申请日：2016-10-25

Applicant: CARL ZEISS SMT GMBH ,  STIEPAN, Hans-Michael ,  ZOTT, Andy ,  MANTZ, Ulrich

Inventor： STIEPAN, Hans-Michael ,  ZOTT, Andy ,  MANTZ, Ulrich

IPC: G03F7/20 ,  G01N21/47 ,  G01N21/95

CPC classification number: G03F7/70625 ,  G01B2210/56 ,  G01N21/4788 ,  G01N21/9501 ,  G01N2021/4735 ,  G01N2021/4792 ,  G03F7/70508 ,  G03F7/70633

Abstract: Die Erfindung betrifft Verfahren und Vorrichtungen zur Charakterisierung eines durch wenigstens einen Lithographieschritt strukturierten Wafers. Gemäß einem Aspekt wird eine Mehrzahl von für den strukturierten Wafer charakteristischen Parametern auf Basis von Messungen der Intensität elektromagnetischer Strahlung nach deren Beugung an dem strukturierten Wafer ermittelt, wobei diese Intensitätsmessungen für wenigstens eine Nutzstruktur und wenigstens eine Hilfsstruktur durchgeführt werden, wobei eine Ermittlung der Parameter basierend auf bei den Intensitätsmessungen für jeweils unterschiedliche Kombinationen aus Wellenlänge, Polarisation und/oder Beugungsordnung gemessenen Intensitätswerten sowie entsprechend berechneten Intensitätswerten unter Anwendung einer mathematischen Optimierungsmethode erfolgt. Die Ermittlung der für den strukturierten Wafer charakteristischen Parameter weist folgende Schritte auf: Ermitteln von Parametern eines ersten Parametersatzes auf Basis der für die wenigstens eine Hilfsstruktur erhaltenen Intensitätswerte, und Ermitteln von Parametern eines zweiten Parametersatzes unter Berücksichtigung der ermittelten Parameter des ersten Parametersatzes.

Abstract translation: 本发明涉及用于表征由至少一个光刻步骤构成的晶片的方法和装置。 宝石＆AUML;大街 r的强度BEAR的测量的基础上图案化的晶片的特征参数;一个方面，多个˚F导航用途的根据图案化晶片上的衍射确定吨电磁辐射，所述强度BEAR tsmessungen˚F导航用途ř至少一种有用的结构和至少一个辅助结构进行导航用途 基于在强度测量中使用数学优化方法分别针对不同的波长组合，极化和/或衍射阶数以及相应计算的强度值测量的强度值来执行参数的确定。 ˚F导航用途的确定r为图案化的晶片的特征参数包括以下步骤：确定˚F导航用途的基础上设定的第一参数的参数R中的至少一个辅助结构获得的强度BEAR tswerte，以及第二组参数的确定参数，并考虑到导航使用帐户所确定的 第一个参数集的参数。

公开(公告)号：WO2016102607A1

公开(公告)日：2016-06-30

申请号：PCT/EP2015/081059

申请日：2015-12-22

Applicant: ASELTA NANOGRAPHICS

Inventor： QUAGLIO, Thomas ,  MILLEQUANT, Mathieu ,  TIPHINE, Charles

IPC: G03F1/20 ,  G03F1/36 ,  G03F7/20

CPC classification number: G03F1/20 ,  G03F1/36 ,  G03F1/78 ,  G03F7/705 ,  G03F7/70508 ,  G03F7/70616

Abstract: The invention discloses an improved method of geometry corrections to be applied to properly transfer semiconductor designs on a wafer or a mask in nanometer scale processes. In contrast with some prior art techniques, geometry corrections and possibly dose corrections are applied before fracturing. Unlike edge based corrections, where the edges are displaced in parallel, the displacements applied to generated geometry corrections according to the invention do not preserve parallelism of the edges, which is specifically well suited for free form designs. A seed design is generated from the target design. Vertices connecting segments are placed along the seed design contour. Correction sites are placed on the segments. Displacement vectors are applied to the vertices. A simulated contour is generated and compared to the contour of the target design. The process is iterated until a match criteria between simulated and target design (or another stop criteria) is reached.

Abstract translation: 本发明公开了一种改进的几何校正方法，其应用于在纳米级工艺中在晶片或掩模上适当地转移半导体设计。 与一些现有技术相反，在压裂之前应用几何校正和可能的剂量校正。 不同于基于边缘的校正，其中边缘平行移位，应用于根据本发明的生成的几何校正的位移不保留边缘的平行度，其特别适合于自由形式设计。 从目标设计生成种子设计。 连接片段的顶点沿种子设计轮廓放置。 校正站点放置在段上。 位移向量应用于顶点。 生成模拟轮廓并与目标设计的轮廓进行比较。 迭代该过程，直到达到模拟和目标设计（或另一个停止标准）之间的匹配标准。

公开(公告)号：WO2012143548A2

公开(公告)日：2012-10-26

申请号：PCT/EP2012057366

申请日：2012-04-23

Applicant: MAPPER LITHOGRAPHY IP BV ,  VAN KERVINCK MARCEL NICOLAAS JACOBUS ,  DE BOER GUIDO

Inventor： VAN KERVINCK MARCEL NICOLAAS JACOBUS ,  DE BOER GUIDO

IPC: H01J37/317

CPC classification number: G06F9/48 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/70483 ,  G03F7/70508 ,  G03F7/70525 ,  G03F7/70991 ,  G05B19/41865 ,  G06F9/4881 ,  H01J37/3177

Abstract: A clustered substrate processing system comprising one or more lithography elements, each lithography element arranged for independent exposure of substrates according to pattern data. Each lithography element comprises a plurality of lithography subsystems, a control network arranged for communication of control information between the lithography subsystems and at least one element control unit, the element control unit arranged to transmit commands to the lithography subsystems and the lithography subsystems arranged to transmit responses to the element control unit. Each lithography element also comprises a cluster front-end for interface to an operator or host system, the front-end arranged for issuing control information to the at least one element control unit to control operation of the one or more lithography subsystems for exposure of one or more wafers. The front-end is arranged for issuing a process program to the element control unit, the process program comprising a set of predefined commands and associated parameters, each command corresponding to a predefined action or sequence of actions to be performed by one or more of the lithography subsystems, and the parameters further defining how the action or sequence of actions are to be performed.

Abstract translation: 包括一个或多个光刻元件的聚集基板处理系统，每个光刻元件被布置成根据图案数据独立地曝光基板。 每个光刻元件包括多个光刻子系统，布置成用于在光刻子系统与至少一个元件控制单元之间传送控制信息的控制网络，所述元件控制单元被布置成将命令传送到光刻子系统和布置成传输的光刻子系统 对元件控制单元的响应。 每个光刻元件还包括用于与操作员或主机系统接口的簇前端，前端被布置为向至少一个元件控制单元发出控制信息，以控制一个或多个光刻子系统的操作以暴露一个 或更多的晶片。 前端被布置成用于向元件控制单元发出处理程序，该处理程序包括一组预定义的命令和相关联的参数，每个命令对应于由一个或多个 光刻子系统，以及进一步定义如何执行动作或动作序列的参数。

公开(公告)号：WO2012046233A2

公开(公告)日：2012-04-12

申请号：PCT/IL2011000779

申请日：2011-10-05

Applicant: ZEISS CARL SMS LTD ,  DMITRIEV VLADIMIR ,  SHARONI OFIR

Inventor： DMITRIEV VLADIMIR ,  SHARONI OFIR

IPC: G03F7/20

CPC classification number: G06F17/5081 ,  G03F7/70508 ,  G03F7/70625

Abstract: Data associated with a substrate can be processed by measuring a property of at least a first type of specific features and a second type of specific features on a substrate. The first type of specific features is measured at a first plurality of locations on the substrate to generate a first group of measured values, and the second type of specific features is measured at a second plurality of locations on the substrate to generate a second group of measured values, in which the first and second groups of measured values are influenced by critical dimension variations of the substrate. A combined measurement function is defined based on combining the at least first and second groups of measured values. At least one group of measured values is transformed prior to combining with another group or other groups of measured values, in which the transformation is defined by a group of coefficients. Variations in the critical dimension across the substrate are determined based on the combined measurement function and a predetermined relationship between the measured values and the critical dimension.

Abstract translation: 可以通过测量衬底上的至少第一类型的特定特征和第二类型的特定特征的性质来处理与衬底相关联的数据。 在衬底上的第一多个位置处测量第一类型的特定特征以生成第一组测量值，并且在衬底上的第二多个位置处测量第二类型的特定特征以生成第二组 测量值，其中第一和第二组测量值受衬底临界尺寸变化的影响。 基于组合测量值的至少第一组和第二组来定义组合测量功能。 至少一组测量值在与另一组或其他组测量值组合之前进行变换，其中变换由一组系数定义。 基于组合的测量函数和测量值与临界尺寸之间的预定关系来确定衬底上的临界尺寸的变化。

公开(公告)号：WO2012031285A1

公开(公告)日：2012-03-08

申请号：PCT/US2011/050459

申请日：2011-09-03

Applicant: PINEBROOK IMAGING SYSTEMS CORPORATION ,  CHEN, Jang, Fung ,  LAIDIG, Thomas

Inventor： CHEN, Jang, Fung ,  LAIDIG, Thomas

IPC: G02B26/00

CPC classification number: G03B27/42 ,  G03F7/70275 ,  G03F7/70283 ,  G03F7/70291 ,  G03F7/70391 ,  G03F7/70433 ,  G03F7/70475 ,  G03F7/70491 ,  G03F7/70508

Abstract: System and method for manufacturing three-dimensional integrated circuits are disclosed. In one embodiment, the method includes providing an imaging writer system that includes a plurality of spatial light modulator (SLM) imaging units arranged in one or more parallel arrays, receiving mask data to be written to one or more layers of the three-dimensional integrated circuit, processing the mask data to form a plurality of partitioned mask data patterns corresponding to the one or more layers of the three-dimensional integrated circuit, assigning one or more SLM imaging units to handle each of the partitioned mask data pattern, and controlling the plurality of SLM imaging units to write the plurality of partitioned mask data patterns to the one or more layers of the three-dimensional integrated circuits in parallel. The method of assigning performs at least one of scaling, alignment, inter-ocular displacement, rotational factor, or substrate deformation correction.

Abstract translation: 公开了用于制造三维集成电路的系统和方法。 在一个实施例中，该方法包括提供一种成像写入器系统，该系统包括布置在一个或多个并行阵列中的多个空间光调制器（SLM）成像单元，接收要写入三维集成的一个或多个层的掩模数据 处理掩模数据以形成与三维集成电路的一层或多层相对应的多个划分的掩模数据模式，分配一个或多个SLM成像单元以处理每个分割的掩模数据模式，并且控制 多个SLM成像单元将多个划分的掩模数据图案并行地写入三维集成电路的一个或多个层。 分配方法执行缩放，对准，眼内位移，旋转因子或基底变形校正中的至少一个。

公开(公告)号：WO2011107603A1

公开(公告)日：2011-09-09

申请号：PCT/EP2011/053337

申请日：2011-03-04

Applicant: MICRONIC MYDATA AB ,  IVANSEN, Lars ,  ÖSTERBERG, Anders

Inventor： IVANSEN, Lars ,  ÖSTERBERG, Anders

IPC: G03F7/20

CPC classification number: G03F7/2051 ,  G03F7/70291 ,  G03F7/70508 ,  G03F7/70541 ,  G06F17/50

Abstract: The present invention relates to customizing individual workpieces, such as chip, flat panels or other electronic devices produced on substrates, by direct writing a custom pattern. Customization can be per device, per substrate, per batch or at some other small volume that makes it impractical to use a custom mask or mask set. In particular, it relates to customizing a latent image formed in a radiation sensitive layer over a substrate, merging standard and custom pattern data to form a custom pattern used to produce the customized latent image. A wide variety of substrates can benefit from the technology disclosed.

Abstract translation: 本发明涉及通过直接写入定制图案来定制单个工件，例如芯片，平板或在基板上制造的其它电子设备。 定制可以是每个设备，每个基板，每个批处理或一些其他小的体积，这使得使用自定义掩码或掩码集不切实际。 特别地，它涉及定制在基底上的辐射敏感层中形成的潜像，合并标准和定制图案数据以形成用于产生定制潜像的定制图案。 各种基板可以从所公开的技术中受益。

公开(公告)号：WO2011075388A1

公开(公告)日：2011-06-23

申请号：PCT/US2010/059677

申请日：2010-12-09

Applicant: PINEBROOK IMAGING SYSTEMS CORPORATION ,  LAIDIG, Thomas

Inventor： LAIDIG, Thomas

IPC: G03B27/42

CPC classification number: G03F7/70275 ,  G03F7/70258 ,  G03F7/70291 ,  G03F7/70508

Abstract: System and method for applying mask data patterns Io substrate in a lithography manufacturing process are disclosed In one embodiment, the method includes providing a parallel imaging writer system having a plurality of spatial light modulator (SLM) imaging units as ranged m one or more parallel arrays receiving a mask data pattern to be written to a substrate, processing the mask data pattern to form a ρlurality of partitioned mask data patterns corresponding to different areas of the substrate, identifying objects in an area of the substrate to be imaged by corresponding SLMs, selecting evaluation points along edges of the objects, configuring the parallel imaging writes system to image the objects using the evaluations points, and performing multiple exposure to image the objects in the area of the substrate by controlling the plurality of SLMs to write the plurality of partitioned mask data patterns m parallel

Abstract translation: 公开了用于在光刻制造工艺中应用掩模数据图案Io衬底的系统和方法。在一个实施例中，该方法包括提供并行成像写入器系统，其具有多个空间光调制器（SLM）成像单元，其范围为一个或多个并行阵列 接收要写入衬底的掩模数据模式，处理掩模数据模式以形成对应于衬底的不同区域的划分的掩模数据模式的光谱，识别要由相应的SLM成像的衬底的区域中的对象， 沿对象的边缘选择评估点，配置并行成像写入系统以使用评估点对对象进行成像，并且通过控制多个SLM来写入多个分区的多个曝光来对基板区域中的对象进行成像 掩模数据模式m并行

公开(公告)号：WO2011044361A1

公开(公告)日：2011-04-14

申请号：PCT/US2010/051823

申请日：2010-10-07

Applicant: PINEBROOK IMAGING SYSTEMS CORPORATION ,  LAIDIG, Thomas

Inventor： LAIDIG, Thomas

IPC: G03F1/00

CPC classification number: G03F7/70291 ,  G03F7/70475 ,  G03F7/70508

Abstract: System and method for processing image data between adjacent imaging areas in a lithography manufacturing process are disclosed, hi one embodiment, the method includes providing a parallel imaging writer system which has a plurality of spatial light modulator (SLM) imaging units arranged in one or more parallel arrays, receiving a mask data pattern to be written to a substrate, processing the mask data pattern to form a plurality of partitioned mask data patterns corresponding to different areas of the substrate, identifying an overlapping region between adjacent imaging areas to be imaged by corresponding SLMs, determining a stitching path for merging the adjacent imaging areas m the overlapping region in accordance with a set of predetermined cost functions, and controlling the plurality of SLM imaging units to write die plurality of partitioned mask data patterns to the substrate in parallel using the stitching path.

Abstract translation: 公开了一种用于在光刻制造过程中在相邻成像区域之间处理图像数据的系统和方法。在一个实施例中，该方法包括提供并行成像写入器系统，其具有布置在一个或多个中的多个空间光调制器（SLM）成像单元 平行阵列，接收要写入衬底的掩模数据模式，处理掩模数据模式以形成对应于衬底的不同区域的多个划分的掩模数据模式，通过相应的识别要成像的相邻成像区域之间的重叠区域 SLM，确定用于根据一组预定的成本函数合并重叠区域中的相邻成像区域的缝合路径，以及控制多个SLM成像单元将多个分割的掩模数据图案写入到基板上，并使用 拼接路径