公开(公告)号：WO2004019384B1

公开(公告)日：2004-12-02

申请号：PCT/US0326906

申请日：2003-08-25

Applicant: MICRON TECHNOLOGY INC

Inventor： LUAN TRAN C

IPC: H01L27/08 ,  A44C7/00 ,  H01L21/00 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  H01L29/10 ,  H01L29/49 ,  H01L29/78 ,  H01L31/062 ,  H01L31/113 ,  H01L21/765 ,  H01L21/8238 ,  H01L27/105

CPC classification number: H01L27/10894 ,  H01L21/28044 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/1041 ,  H01L29/4916 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/78 ,  Y10S438/919 ,  Y10S438/975

Abstract: The invention includes a semiconductor construction wherein gate structures are separated by isolation regions that are provided with an indium-doped pocket and a covering gate. The invention also includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying sub-regions. The invention also includes a semiconductor construction that has transistor constructions with insulative spacers along gate sidewalls. Each transistor construction is between a pair source/drain regions that extend beneath the spacers. A source/drain extension extends the source/drain region farther beneath the transistor constructions on only one side of each of the transistor constructions. The invention also includes methods of forming semiconductor constructions.

Abstract translation: 本发明包括半导体结构，其中栅极结构由设置有铟掺杂口袋和覆盖栅极的隔离区隔开。 本发明还包括具有一对沟道区域的半导体结构，该沟道区域具有被铟掺杂并被硼包围的子区域。 一对晶体管结构位于沟道区上方并由隔离区隔开。 晶体管具有比下面的子区域更宽的栅极。 本发明还包括半导体结构，其具有在栅极侧壁处具有绝缘间隔物的晶体管结构。 每个晶体管结构位于在间隔物下方延伸的一对源/漏区之间。 源极/漏极扩展器在仅在晶体管结构中的每一个的一侧上的晶体管结构之下延伸更远的源极/漏极区域。 本发明还包括形成半导体结构的方法。

公开(公告)号：WO1996004679A1

公开(公告)日：1996-02-15

申请号：PCT/US1995009510

申请日：1995-07-28

Applicant: NATIONAL SEMICONDUCTOR CORPORATION

Inventor： NATIONAL SEMICONDUCTOR CORPORATION ,  KAO, Dah-Bin ,  SCOTT, Gregory, S.

IPC: H01L21/265

CPC classification number: H01L29/66492 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7836 ,  Y10S438/919

Abstract: A method of processing a semiconductor device shapes a layer buried within a substrate of the semiconductor device. This layer has a conductivity the same as that of the substrate but has a higher doping level. In this process, a region of the layer is selected and ions of an opposite conductivity to the selected layer are counter-implanted in the region so that the doping level is substantially canceled. A region of the layer adjacent to the counter-implanted region retains a higher doping level. Alternative techniques are employed to protect the doped region against the counter-implant. In a first approach, the layer is doped and subsequently a mask is formed on the surface of the substrate. The mask is furnished by a part of the semiconductor device, such as a spacer which is connected to the gate electrode after the dopant layer is formed in the substrate. After the mask is formed, ions are counter-implanted with the mask protecting the doped region. In a second approach, both the ion implant forming the doped layer and the counter-implant are performed after masking structures are formed, however the ion implant is a large-angle implant which implants ions beneath the masking structure while the counter-implant is a perpendicular implant so that regions beneath the masking structure are protected from cancellation.

Abstract translation: 半导体器件的处理方法对埋在半导体器件的衬底内的层进行成形。 该层具有与衬底相同的导电性，但具有较高的掺杂水平。 在该过程中，选择该层的区域，并且与所选择的层具有相反电导率的离子在该区域中相对注入，使得掺杂水平基本上被消除。 与反注入区相邻的层的区域保持较高的掺杂水平。 采用替代技术来保护掺杂区域免受反向植入。 在第一种方法中，该层被掺杂，随后在衬底的表面上形成掩模。 掩模由半导体器件的一部分提供，例如在衬底中形成掺杂剂层之后连接到栅电极的间隔物。 在形成掩模之后，用保护掺杂区域的掩模对离子进行反注入。 在第二种方法中，形成掺杂层和对置注入的离子注入都是在形成掩模结构之后进行的，然而离子注入是在掩模结构下面植入离子的大角度注入，而反植入物是 使得掩蔽结构下面的区域被保护而不被抵消。

公开(公告)号：WO2004019384A2

公开(公告)日：2004-03-04

申请号：PCT/US2003/026906

申请日：2003-08-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： LUAN, Tran, C.

IPC: H01L

CPC classification number: H01L27/10894 ,  H01L21/28044 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/1041 ,  H01L29/4916 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/78 ,  Y10S438/919 ,  Y10S438/975

Abstract: The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying sub-regions. The invention also includes a semiconductor construction that has transistor constructions with insulative spacers along gate sidewalls. Each transistor construction is between a pair source/drain regions that extend beneath the spacers. A source/drain extension extends the source/drain region farther beneath the transistor constructions on only one side of each of the transistor constructions. The invention also includes methods of forming semiconductor constructions.

Abstract translation: 本发明包括具有一对沟道区的半导体结构，所述沟道区具有被铟掺杂并被硼包围的子区。 一对晶体管结构位于沟道区上方并由隔离区隔开。 晶体管具有比下面的子区域更宽的栅极。 本发明还包括半导体结构，其具有在栅极侧壁处具有绝缘间隔物的晶体管结构。 每个晶体管结构位于在间隔物下方延伸的一对源/漏区之间。 源极/漏极扩展器在仅在晶体管结构中的每一个的一侧上的晶体管结构之下的源极/漏极区域延伸得更远。 本发明还包括形成半导体结构的方法。

公开(公告)号：WO1987002825A1

公开(公告)日：1987-05-07

申请号：PCT/GB1986000675

申请日：1986-10-31

Applicant: PLESSEY OVERSEAS LIMITED ,  FOSTER, David, John ,  PICKERING, Andrew, James

Inventor： PLESSEY OVERSEAS LIMITED

IPC: H01L21/225

CPC classification number: H01L29/6659 ,  H01L21/22 ,  H01L21/2255 ,  H01L29/78 ,  H01L29/7836 ,  Y10S438/919

Abstract: A method for producing MOS transistors of the type having shallow, lightly doped, source/drain structure. In this method sidewall fillets (7) of n-type doped dielectric material are defined adjacent to the sides of the oxide (1) and metal electrode (3) features. These fillets (7) are then employed to provide self aligned masking during implantation of heavy dopant of either n- or p-type (9; 13). In a subsequent rapid anneal step, the implant dopant is activated and n-type dopant diffused into the substrate (5) from the fillets (7) to provide lightly doped source/drain structures (11; 15). Examples of this method are described for producing phosphorous-arsenic n /n and phosphorus-boron p /p source/drain structures.

Abstract translation: 一种用于制造具有浅的，轻掺杂的源极/漏极结构的类型的MOS晶体管的方法。 在该方法中，n型掺杂电介质材料的侧壁片（7）与氧化物（1）和金属电极（3）的侧面相邻地限定。 然后使用这些圆角（7）在植入n型或p型（9; 13）的重掺杂物期间提供自对准掩蔽。 在随后的快速退火步骤中，注入掺杂剂被激活，并且n型掺杂剂从焊脚（7）扩散到衬底（5）中以提供轻掺杂的源/漏结构（11; 15）。 描述了用于产生磷 - 砷/ n +和磷 - 硼p - / p +源/漏结构的该方法的实例。

公开(公告)号：WO1990002416A1

公开(公告)日：1990-03-08

申请号：PCT/FR1989000423

申请日：1989-08-17

Applicant: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE ... ,  ETAT FRANÇAIS, représenté par LE MINISTRE DELEGUE ,  ROSE, Benoît ,  MIRCEA, Andréi ,  CHEVALLIER, Jacques ,  PESANT, Jean-Claude

Inventor： CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE ... ,  ETAT FRANÇAIS, représenté par LE MINISTRE DELEGUE

IPC: H01L21/324

CPC classification number: H01L21/7605 ,  H01L21/02392 ,  H01L21/02461 ,  H01L21/02546 ,  H01L21/02579 ,  H01L21/02581 ,  H01L21/02694 ,  H01L21/2654 ,  H01L21/3245 ,  Y10S438/919 ,  Y10S438/925

Abstract: The method disclosed comprises the epitaxing of a layer (4) of p doped InP and a layer (6) of Ga0.47In0.53As non intentionally doped on a semi-insolating substrate (2) of InP, and hydrogenating the InP layer by subjecting the assembly to a hydrogen plasma (8) having a power density smaller than 0.07 W/cm or at the most equal to 250 DEG C.

Abstract translation: 所公开的方法包括：在InP的半剥离衬底（2）上有意掺杂的p掺杂InP的层（4）和GaI.47In0.53As（6）的表层，并且通过使InP层 组装到功率密度小于0.07W / cm 2或至多等于250℃的氢等离子体（8）

公开(公告)号：WO1985004759A1

公开(公告)日：1985-10-24

申请号：PCT/US1985000502

申请日：1985-03-25

Applicant: AMERICAN TELEPHONE & TELEGRAPH COMPANY

Inventor： AMERICAN TELEPHONE & TELEGRAPH COMPANY ,  OH, Kye, Hwan

IPC: H01L21/22

CPC classification number: H01L21/28512 ,  H01L21/2257 ,  Y10S148/035 ,  Y10S438/919 ,  Y10S438/923

Abstract: In semiconductor devices of extremely small dimensions, the problem of shorting together of adjacent, differently doped regions (12, 14) by a contact layer deposited through a window (17) which, owing to the smallness of the region dimensions, unavoidably exposes a surface portion of the adjacent region (12) not intended to be contacted, is solved by the use of a transfer layer (18) deposited first in the window which, upon heating, transfers impurities from the region (14) intended to be contacted to the unintentionally exposed portion of the adjacent region (12). The transferred impurities convert the exposed portion of the adjacent region to the same conductivity type as the impurity source region (14), thereby preventing shorting together of the contacted region (14) with the remaining, unconverted portion of the adjacent region.

Abstract translation: 在极小尺寸的半导体器件中，由通过窗口（17）沉积的接触层使相邻的不同掺杂区域（12,14）短路在一起的问题，由于区域尺寸的小，不可避免地暴露出表面 通过使用首先沉积在窗口中的转移层（18）来解决邻近区域（12）中未被接触的部分，该转移层（18）在加热时将来自预期接触的区域（14）的杂质转移到 相邻区域（12）的无意曝光部分。 所转移的杂质将相邻区域的暴露部分转换为与杂质源区域（14）相同的导电类型，从而防止接触区域（14）与相邻区域的剩余的未转换部分短路在一起。

公开(公告)号：WO2004019384A3

公开(公告)日：2004-09-16

申请号：PCT/US0326906

申请日：2003-08-25

Applicant: MICRON TECHNOLOGY INC

Inventor： LUAN TRAN C

IPC: H01L27/08 ,  A44C7/00 ,  H01L21/00 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  H01L29/10 ,  H01L29/49 ,  H01L29/78 ,  H01L31/062 ,  H01L31/113 ,  H01L21/765 ,  H01L21/8238 ,  H01L27/105

CPC classification number: H01L27/10894 ,  H01L21/28044 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/1041 ,  H01L29/4916 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/78 ,  Y10S438/919 ,  Y10S438/975

Abstract: The invention includes a semiconductor construction wherein gate structures are separated by isolation regions that are provided with an indium-doped pocket and a covering gate. The invention also includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying sub-regions. The invention also includes a semiconductor construction that has transistor constructions with insulative spacers along gate sidewalls. Each transistor construction is between a pair source/drain regions that extend beneath the spacers. A source/drain extension extends the source/drain region farther beneath the transistor constructions on only one side of each of the transistor constructions. The invention also includes methods of forming semiconductor constructions.

Abstract translation: 本发明包括一种半导体结构，其中栅极结构被设置有铟掺杂袋和覆盖栅的隔离区隔开。 本发明还包括具有一对沟道区域的半导体构造，该沟道区域具有掺杂有铟且被硼包围的子区域。 一对晶体管结构位于沟道区上方并且被隔离区分开。 晶体管的栅极比下面的子区域宽。 本发明还包括具有沿着栅极侧壁具有绝缘隔离物的晶体管结构的半导体构造。 每个晶体管结构位于在间隔器下方延伸的一对源极/漏极区域之间。 源极/漏极延伸仅在每个晶体管结构的一侧上将晶体管结构下方的源极/漏极区域延伸得更远。 本发明还包括形成半导体构造的方法。

公开(公告)号：WO00022681A1

公开(公告)日：2000-04-20

申请号：PCT/AU1999/000871

申请日：1999-10-12

IPC: H01L21/28 ,  H01L21/268 ,  H01L31/0224 ,  H01L31/0352 ,  H01L31/04 ,  H01L31/18 ,  H01L31/20

CPC classification number: H01L31/1804 ,  H01L31/022425 ,  H01L31/03529 ,  Y02E10/547 ,  Y02P70/521 ,  Y10S438/919

Abstract: A thin film photovoltaic device is described, having a glass substrate 11 over which is formed a thin film silicon device having an n layer 12, a p layer 13 and a dielectric layer 14 (typically silicon oxide or silicon nitride). To create a connection through the p layer 13 to the underlying n layer 12, a column of semi-conductor material is heated, the column passing through the various doped layers and the material in the column being heated or melted to allow migration of dopant between layers of the device in the region of the column.

Abstract translation: 描述了一种薄膜光伏器件，其具有形成有具有n ++层12，p层13和介电层14（通常为氧化硅或氮化硅）的薄膜硅器件的玻璃衬底11。 为了创建通过p层13到底层n ++层12的连接，加热一列半导体材料，该柱通过各种掺杂层，并且柱中的材料被加热或熔化以允许 在柱的区域中的器件的层之间的掺杂剂迁移。

公开(公告)号：WO1997023901A1

公开(公告)日：1997-07-03

申请号：PCT/IB1996001334

申请日：1996-12-03

Applicant: PHILIPS ELECTRONICS N.V. ,  PHILIPS NORDEN AB

Inventor： PHILIPS ELECTRONICS N.V. ,  PHILIPS NORDEN AB ,  LUDIKHUIZE, Adrianus, Willem

IPC: H01L21/225

CPC classification number: H01L29/0852 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/7813 ,  H01L29/7824 ,  Y10S438/919

Abstract: An epitaxial layer with a doping of approximately 10 atoms per cm is used in accordance with the resurf condition for the high-voltage circuit element in high-voltage integrated circuits of the resurf type. If the circuit comprises a zone which is provided in the epitaxial layer, which is of the same conductivity type as the substrate, and to which a high voltage is applied, the doping between this zone and the substrate must in addition be sufficiently high for preventing punch-through between the zone and the substrate. A known method of complying with these two requirements is to make the epitaxial layer very thick. It is found in practice, however, that this method is often not very well reproducible. According to the invention, the epitaxial layer is provided in the form of a high-ohmic layer which is doped from the upper side (3a) and from a buried layer (3b). The buried layer is blanket-deposited, which dispenses with a masking step, and is locally redoped by the island insulation zone (4).

Abstract translation: 根据resurf型高压集成电路中的高电压电路元件的再生条件，使用每cm 2掺杂约10 12个原子的外延层。 如果电路包括设置在与衬底相同的导电类型的外延层中并且施加高电压的区域，则该区域和衬底之间的掺杂必须另外足够高以防止 在区域和基底之间穿透。 符合这两个要求的已知方法是使外延层非常厚。 然而，在实践中发现，该方法通常不是非常好的重现性。 根据本发明，外延层以从上侧（3a）和掩埋层（3b）掺杂的高欧姆层的形式提供。 掩埋层被覆盖沉积，其不需要掩蔽步骤，并且被岛绝缘区（4）局部重新加工。