利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

111 条记录 (耗时 0.013 秒)

    Local interconnect for integrated circuits
    92.
    发明公开
    Local interconnect for integrated circuits 失效
    集成电路的本地互连

    公开(公告)号：EP0517368A3

    公开(公告)日：1993-06-02

    申请号：EP92303974.7

    申请日：1992-05-01

    申请人： SGS-THOMSON MICROELECTRONICS, INC.

    发明人： Chen, Fusen ,  Liou, Fu-Tai ,  Dixit, Girish

    IPC分类号： H01L21/90 ,  H01L23/485 ,  H01L21/3205

    CPC分类号： H01L23/53257 ,  H01L21/76889 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S257/915 ,  H01L2924/00

    摘要： A method for fabrication of local interconnects in an integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to the disclosed embodiment, a first and a second conductive structure are formed over the integrated circuit. An insulating layer (28) is formed over the integrated. A first photoresist layer is formed over the insulating layer, patterned and developed. The insulating layer is etched to expose selected regions of the first and second conductive structures. A refractory metal layer (30) is formed over the integrated circuit. A barrier layer (32) is formed over the refractory metal layer, and optionally a refractory metal silicide layer (34) is formed over the barrier layer. A second photoresist layer is formed over the barrier layer, patterned and developed. The refractory metal layer and barrier layer, and the refractory metal silicide layer if formed, are etched to define a conductive interconnect between the exposed selected regions of the first and second conductive structures.

    Method of manufacturing a semiconductor device whereby a self-aligned cobalt or nickel silicide is formed
    93.
    发明公开
    Method of manufacturing a semiconductor device whereby a self-aligned cobalt or nickel silicide is formed 失效
    一种制造半导体器件，其特征在于，形成有自注册钴或硅化镍的方法。

    公开(公告)号：EP0501561A1

    公开(公告)日：1992-09-02

    申请号：EP92200459.3

    申请日：1992-02-18

    申请人： Philips Electronics N.V.

    发明人： Duchateau, John Philippe William ,  Reader, Alec Harold ,  van der Kolk, Gerrit Jan

    IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/3205

    CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/76889 ,  H01L29/665 ,  H01L29/7848 ,  Y10S148/019 ,  Y10S148/147 ,  Y10S438/934

    摘要： A method of manufacturing a semiconductor device whereby a layer (12) containing Co or Ni is deposited on a surface (2) of a semiconductor body (1) bounded by silicon regions (3, 4, 5, 6) and regions of insulating material (8, 9), after which the semiconductor body (1) is heated during a heat treatment to a temperature at which the Co or Ni does form a metal silicide with the silicon (3, 4, 5, 6), but not with the insulating material (8, 9). On the surface (2) of the layer (12) containing the Co or Ni, according to the invention, a layer of an amorphous alloy of this metal with a metal from a group comprising Ti, Zr, Ta, Mo, Nb, Hf and W is deposited, while furthermore the temperature is so adjusted during the heat treatment that the layer (12) of the amorphous alloy remains amorphous during the heat treatment. In this way a metal silicide is formed on the silicon regions (3, 4, 5, 6) only and not on the regions of insulating material (8, 9) directly adjoining them, in other words, the method yields a self-aligned metal silicide.

    摘要翻译： 一种制造半导体器件，从而包含Co或Ni的层（12）的表面上沉积的方法，（2）由硅区（3，4，5，6）和绝缘材料的区域限定的半导体主体（1）的 （8，9），afterwhich半导体本体（1）的热处理在其中Co或Ni确实形成与硅（3，4，5，6），但不与金属硅化物的温度时被加热 绝缘材料（8，9）。 上的层（12），其含有Co或Ni，雅丁到本发明，该金属与选自包括钛，锆，钽，钼，铌，铪金属的无定形合金的层的表面（2） 和W被沉积，而进一步更的温度，以便在热处理过程中进行调整，DASS死非晶合金的层（12）保持在热处理过程中无定形的。 以这种方式，金属硅化物上的硅区域形成（3，4，5，6），而不是在绝缘材料的区域（8,9）直接邻接他们，换句话说，该方法产生自对准的 金属硅化物。

    Contact structure for connecting electrode to a semiconductor device and a method of forming the same
    95.
    发明公开
    Contact structure for connecting electrode to a semiconductor device and a method of forming the same 失效
    用于将电极连接到半导体器件的接触结构及其形成方法

    公开(公告)号：EP0343667A3

    公开(公告)日：1991-04-17

    申请号：EP89109461.7

    申请日：1989-05-26

    申请人： FUJITSU LIMITED

    发明人： Nishida, Kenji ,  Sato, Noriaki

    IPC分类号： H01L23/48 ,  H01L21/60 ,  H01L21/283

    CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L23/485 ,  H01L23/53257 ,  H01L29/665 ,  H01L2924/0002 ,  Y10S148/019 ,  H01L2924/00

    摘要： A contact structure for connecting a semiconductor device to a wiring electrode comprises a semiconductor layer (11) forming a part of the semiconductor device, a first contact layer (17a) of reduced resistivity for covering a surface of the semiconductor layer, an insulating structure (18, 19) provided on the first contact layer so as to bury the first contact layer underneath, a penetrating hole (20) opened through the insulating structure so as to expose a part of the first contact layer, a second contact layer (17b) of reduced resistivity provided on the part of the first contact layer exposed by the penetrating hole, in which the second contact layer extends from a bottom of the penetrating hole along its side wall, and a conductor layer (22) forming the wiring electrode provided on the second contact layer.

    摘要翻译： 用于将半导体器件连接到布线电极的接触结构包括形成半导体器件的一部分的半导体层（11），用于覆盖半导体层的表面的电阻率降低的第一接触层（17a），绝缘结构 18，19）设置在第一接触层上，以便在其下方埋设第一接触层，穿过绝缘结构开放的穿透孔（20）以露出第一接触层的一部分，第二接触层（17b） 所述第一接触层暴露在所述第一接触层的部分上的所述第一接触层的第二接触层沿着其侧壁从所述穿透孔的底部延伸，并且形成所述布线电极的导体层， 第二接触层。

    Local interconnect for integrated circuits
    96.
    发明公开
    Local interconnect for integrated circuits 失效
    Lokalverbindungenfürintegrierte Schaltungen。

    公开(公告)号：EP0400821A2

    公开(公告)日：1990-12-05

    申请号：EP90304926.0

    申请日：1990-05-08

    申请人： SGS-THOMSON MICROELECTRONICS, INC.

    发明人： Liou, Fu-Tai ,  Lin, Yih-Shung ,  Chen, Fusen E.

    IPC分类号： H01L29/62 ,  H01L21/60

    CPC分类号： H01L29/6659 ,  H01L21/28518 ,  H01L21/32155 ,  H01L21/76895 ,  H01L23/53271 ,  H01L29/78 ,  H01L2924/0002 ,  Y10S148/015 ,  Y10S148/019 ,  Y10S148/02 ,  H01L2924/00

    摘要： A silicide layer, to improve conductivity, is formed over a first layer of polycrystalline silicon, followed by a second layer of polycrystalline silicon. This structure is then patterned to form gate regions over active areas. A layer of metal silicide is formed over the entire surface of the chip, and patterned to form local interconnect. Etching of the second metal silicide layer is stopped by the second polycrystalline silicon layer, thereby protecting the first metal silicide layer from damage.

    摘要翻译： 在第一层多晶硅上形成硅化物层，以提高导电性，随后是第二层多晶硅。 然后将该结构图案化以在有效区域上形成栅极区域。 在芯片的整个表面上形成金属硅化物层，并且被图案化以形成局部互连。 通过第二多晶硅层阻止第二金属硅化物层的蚀刻，从而保护第一金属硅化物层免受损坏。