公开(公告)号：EP2988204A1

公开(公告)日：2016-02-24

申请号：EP14814662.4

申请日：2014-04-30

申请人： Huawei Technologies Co., Ltd.

发明人： LI, Yansong ,  ZHENG, Yulin

IPC分类号： G06F3/06

CPC分类号： G06F13/4234 ,  G06F13/4027

摘要： Embodiments of the present application disclose a memory extension system and method. The system includes a processor, an extended memory, an extended chip, and multiple processor installation positions, where a memory installation position is provided in each processor installation position; the multiple processor installation positions are connected through a QuickPath Interconnect QPI interface, the processor is installed in at least one processor installation position, and at least one of the other processor installation positions is used as an extended installation position; the extended chip is installed in at least one extended installation position; and the extended memory is installed in a memory installation position that is connected to the extended chip. In this memory extension system, an extended chip is installed in another processor installation position to replace a processor, so that an existing processor can access an extended memory of the extended chip by using the extended chip. Thereby, a memory capacity of the existing processor increases while a processing capability does not increase, which resolves a problem of processing capability redundancy caused due to that a processor is added to extend memory.

摘要翻译： 本申请的实施例公开了一种存储器扩展系统和方法。 该系统包括处理器，扩展存储器，扩展芯片和多个处理器安装位置，其中在每个处理器安装位置提供存储器安装位置; 多处理器安装位置通过QuickPath Interconnect QPI接口连接，处理器安装在至少一个处理器安装位置，并且其他处理器安装位置中的至少一个用作扩展安装位置; 延长的芯片安装在至少一个扩展安装位置; 并且扩展存储器安装在连接到扩展芯片的存储器安装位置。 在该存储器扩展系统中，扩展芯片安装在另一个处理器安装位置以替换处理器，使得现有处理器可以通过使用扩展芯片来访问扩展芯片的扩展存储器。 因此，现有处理器的存储器容量增加，而处理能力不增加，这解决了由于添加了处理器而延长存储器而导致的处理能力冗余的问题。

公开(公告)号：EP2973571A1

公开(公告)日：2016-01-20

申请号：EP13877923.6

申请日：2013-03-15

申请人： Intel Corporation

发明人： NALE, Bill ,  JASPER, Jonathan C. ,  LOVELACE, John V. ,  NACHIMUTHU, Murugasamy K. ,  ZHU, Jun ,  QUACH, Tuan M.

IPC分类号： G11C7/10 ,  G11C7/22 ,  G06F13/14

CPC分类号： G06F11/0793 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F12/023 ,  G06F12/0802 ,  G06F12/0813 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/1044 ,  G06F2212/2532 ,  G06F2212/60 ,  G11C5/04 ,  G11C5/148 ,  G11C7/1003 ,  G11C7/1063 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/40618 ,  G11C29/023 ,  G11C29/028 ,  H04L9/0869

摘要： Provided is a device for use in a memory module coupled to a host memory controller over a bus, comprising memory module control logic to generate a request signal to a host memory controller having a pulse width greater than or equal to a minimum pulse width, wherein the minimum pulse width comprises a number of clock cycles needed to guarantee that the host memory controller detects the request signal, and wherein the pulse width of the request signal indicates at least one function in addition to the request signal to the host memory controller.

摘要翻译： 提供一种用于通过总线耦合到主机存储器控制器的存储器模块中的设备，包括存储器模块控制逻辑，用于产生请求信号到主机存储器控制器，该主机存储器控制器具有大于或等于最小脉冲宽度的脉冲宽度，其中 最小脉冲宽度包括保证主机存储器控制器检测请求信号所需的多个时钟周期，并且其中请求信号的脉冲宽度除了向主机存储器控制器提供请求信号之外还指示至少一个功能。

公开(公告)号：EP2801032A4

公开(公告)日：2015-07-01

申请号：EP12864332

申请日：2012-01-04

申请人： INTEL CORP

发明人： CRETA KENNETH C ,  HORIHAN JASON W ,  BLANKENSHIP ROBERT G ,  CHENG KAI

IPC分类号： G06F13/14 ,  G06F3/06 ,  G06F12/00 ,  G06F13/16 ,  G06F13/42 ,  G06F15/80 ,  G11C13/00 ,  G11C14/00

CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/0679 ,  G06F13/16 ,  G06F13/4234 ,  G06F2206/1014 ,  G11C13/0002 ,  G11C14/009

摘要： Methods and apparatus relating to provide bimodal functionality between a coherent link and memory expansion are described. In one embodiment, a processor is coupled to one or more agents via a coherent interconnect. The processor is also coupled to one or more Dual Inline Memory Modules (DIMMs) via a link logic. The logic supports read or write commands directed at the one or more DIMMs based on a single bit of data. Other embodiments are also disclosed and claimed.

公开(公告)号：EP2767908A1

公开(公告)日：2014-08-20

申请号：EP14168733.5

申请日：2009-10-27

申请人： Silicon Image, Inc.

发明人： Ruberg, Alan ,  Lee, Seung-jong ,  Lee, Hyung, Rok ,  Shim, Daeyun ,  Lee, Dongyun ,  Kim, Sungjoon ,  Murthy, Anu

IPC分类号： G06F13/42 ,  G06F11/16

CPC分类号： G11C7/1075 ,  G06F11/141 ,  G06F11/1443 ,  G06F13/1663 ,  G06F13/4234 ,  G11C5/066 ,  Y02D10/14 ,  Y02D10/151

摘要： A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.

摘要翻译： 用于减少存储器等待时间的方法，装置和系统是游离缺失盘。 在一个实施例中，主机计算机系统和存储器之间的数据经由端口或在存储在多个时间间隔一组端口，worin主机计算机耦合至存储器传送。 此外，与数据相关联的命令的主计算机系统和通过端口存储器或在单个时间间隔的组端口之间传送。

公开(公告)号：EP1151387B2

公开(公告)日：2014-07-23

申请号：EP00975263.5

申请日：2000-10-16

申请人： Rambus Inc.

发明人： HOROWITZ, Mark, A. ,  BARTH, Richard M. ,  HAMPEL, Craig, E. ,  MONCAYO, Alfredo ,  DONNELLY, Kevin, S. ,  ZERBE, Jared, L.

IPC分类号： G06F13/14 ,  H03K19/0175

CPC分类号： G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

摘要： Bus communications are optimized by adjusting signal characteristics in accordance with one or more topography dependent parameters. In a bus transmitter a transmit signal characteristic is adjusted in accordance with a topography dependent parameter. A port in the bus transmitter receives the topograpy dependent parameter for later use by the parameter adjustment circuitry. The parameter adjustment circuitry adjusts a parameter control signal in accordance with the topography dependent parameter, which is coupled to the out-put driver. Prior to driving an output signal onto a bus, the output driver adjusts the transmit signal characteristics in accordance with the parameter control signal. In a bus receiver, a receive signal characteristic is also adjusted in accordance with a topography dependent parameter. A port associated with the bus receiver receives the topography dependent parameter and stores it in a register. Parameter adjustment circuitry adjusts a control signal in accordance with the stored topography dependent parameter. An input buffer receives an input signal from a bus coupling the receiver to a transmitter of the input signal. The input buffer generates a first signal from the input signal by adjusting a parameter of the input signal in accordance with the control signal.

摘要翻译： 通过根据一个或多个地形相关参数调整信号特性来优化总线通信。 在总线发射机中，发射信号特性根据地形相关参数进行调整。 总线发射机中的一个端口接收参数调整电路以供以后使用的地理学依赖参数。 参数调整电路根据与输出驱动器耦合的地形相关参数来调整参数控制信号。 在将输出信号驱动到总线之前，输出驱动器根据参数控制信号调整发送信号特性。 在总线接收机中，接收信号特性也根据地形相关参数进行调整。 与总线接收器相关联的端口接收地形相关参数并将其存储在寄存器中。 参数调整电路根据所存储的地形相关参数调整控制信号。 输入缓冲器接收来自将接收器耦合到输入信号的发射器的总线的输入信号。 输入缓冲器根据控制信号通过调节输入信号的参数从输入信号产生第一信号。

公开(公告)号：EP2583280A4

公开(公告)日：2014-06-18

申请号：EP11796154

申请日：2011-06-01

申请人： RAMBUS INC

发明人： WILSON JOHN ,  KIM JOONG-HO ,  KOLLIPARA RAVINDRANATH ,  SECKER DAVID ,  OH KYUNG SUK

IPC分类号： G11C7/10 ,  G06F13/40

CPC分类号： G06F13/4086 ,  G06F13/4234

公开(公告)号：EP2673713A1

公开(公告)日：2013-12-18

申请号：EP12744797.7

申请日：2012-02-08

申请人： Diablo Technologies Inc.

发明人： TAKEFMAN, Michael L. ,  AMER, Maher ,  BADALONE, Riccardo

IPC分类号： G06F13/38 ,  G06F12/02 ,  G06F15/18

CPC分类号： G06F3/0659 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F9/4406 ,  G06F11/1016 ,  G06F11/1076 ,  G06F12/0246 ,  G06F12/0607 ,  G06F13/20 ,  G06F13/404 ,  G06F13/4221 ,  G06F13/4234 ,  G06F13/4282 ,  G06F2212/1008 ,  G06F2212/1032 ,  G06F2212/7201 ,  G06F2212/7208 ,  H03M13/05 ,  H03M13/27 ,  H04L9/0662

摘要： A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.

摘要翻译： 一种用于与协处理器或输入/输出设备的接口系统被游离缺失盘。 。根据一个实施方式，该系统包括一个计算机处理单元，存储器模块，存储器总线没有连接计算机处理单元和所述存储器模块和协处理单元或输入/输出设备，worin存储器总线，以便连接所述 协处理单元或输入/输出设备连接至计算机的处理单元。

公开(公告)号：EP2539823A4

公开(公告)日：2013-07-31

申请号：EP10846793

申请日：2010-11-23

申请人： RAMBUS INC

发明人： SHAEFFER IAN

IPC分类号： G06F13/16

CPC分类号： G06F13/1694 ,  G06F13/287 ,  G06F13/3625 ,  G06F13/4221 ,  G06F13/4234

摘要： A memory controller accesses different types of memory devices running at different native rates through the use of a time division multiplexed bus. Data is transferred over the bus at one rate when accessing one type of memory device and at a different rate when accessing another type of memory device. In addition, the memory controller may provide control information (e.g., command and address information) to the different types of memory devices at different rates and, in some cases, time multiplex the control information on a shared bus.

公开(公告)号：EP2583280A2

公开(公告)日：2013-04-24

申请号：EP11796154.0

申请日：2011-06-01

申请人： Rambus Inc.

发明人： WILSON, John ,  KIM, Joong-Ho ,  KOLLIPARA, Ravindranath ,  SECKER, David ,  OH, Kyung, Suk

IPC分类号： G11C7/10

CPC分类号： G06F13/4086 ,  G06F13/4234

摘要： Termination of a high-speed signaling link is effected by simultaneously engaging on- die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link.

公开(公告)号：EP2273379B1

公开(公告)日：2012-09-19

申请号：EP10180625.5

申请日：2000-10-16

申请人： Rambus Inc.

发明人： Horowitz, Mark A. ,  Barth, Richard M. ,  Hampel, Craig E. ,  Moncayo, Alfredo ,  Donnelly, Kevin S. ,  Zerbe, Jared L.

IPC分类号： G06F13/40 ,  G06F13/16

CPC分类号： G06F13/4291 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F13/102 ,  G06F13/1689 ,  G06F13/364 ,  G06F13/4072 ,  G06F13/4086 ,  G06F13/4234 ,  G06F13/4243 ,  G06F2206/1014 ,  G06F2212/7201 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C19/00 ,  H03K19/00384 ,  H03K19/018585

摘要： Bus communications are optimized by adjusting signal characteristics in accordance with one or more topography dependent parameters. In a bus transmitter a transmit signal characteristic is adjusted in accordance with a topography dependent parameter. A port in the bus transmitter receives the topograpy dependent parameter for later use by the parameter adjustment circuitry. The parameter adjustment circuitry adjusts a parameter control signal in accordance with the topography dependent parameter, which is coupled to the out-put driver. Prior to driving an output signal onto a bus, the output driver adjusts the transmit signal characteristics in accordance with the parameter control signal. In a bus receiver, a receive signal characteristic is also adjusted in accordance with a topography dependent parameter. A port associated with the bus receiver receives the topography dependent parameter and stores it in a register. Parameter adjustment circuitry adjusts a control signal in accordance with the stored topography dependent parameter. An input buffer receives an input signal from a bus coupling the receiver to a transmitter of the input signal. The input buffer generates a first signal from the input signal by adjusting a parameter of the input signal in accordance with the control signal.

摘要翻译： 通过根据一个或多个地形相关参数调整信号特性来优化总线通信。 在总线发射机中，发射信号特性根据地形相关参数进行调整。 总线发射机中的一个端口接收参数调整电路以供以后使用的地理学依赖参数。 参数调整电路根据与输出驱动器耦合的地形相关参数来调整参数控制信号。 在将输出信号驱动到总线之前，输出驱动器根据参数控制信号调整发送信号特性。 在总线接收机中，接收信号特性也根据地形相关参数进行调整。 与总线接收器相关联的端口接收地形相关参数并将其存储在寄存器中。 参数调整电路根据所存储的地形相关参数调整控制信号。 输入缓冲器接收来自将接收器耦合到输入信号的发射器的总线的输入信号。 输入缓冲器根据控制信号通过调节输入信号的参数从输入信号产生第一信号。