公开(公告)号：EP2069814A1

公开(公告)日：2009-06-17

申请号：EP07820965.7

申请日：2007-10-05

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE

发明人： HERON, Olivier ,  BONHOMME, Yannick

IPC分类号： G01R31/3185 ,  G01R31/30

CPC分类号： G01R31/3004 ,  G01R31/318541

摘要： The present invention relates to a parametric scan register. It also relates to a method for testing a digital circuit using such a register. The parametric scan register includes a memory cell (21) having at least one data input (d) capable of receiving test data (e_scan) and transferring to its outlet (s) a signal (62) representative of the input data using a timing signal (h). It further includes a parametric test block (42) having an input connected to the output (s) of the cell (21), the output signal (62) of the cell being transferred to the output (s_reg) of the block (42) through an inner module (61), said inner module operating according to modes capable of modifying the output signal (62) of the cell. The invention is particularly useful for testing integrated circuits having a high integration density, e.g. in the field of nanotechnologies.

公开(公告)号：EP1939641B1

公开(公告)日：2009-06-10

申请号：EP06026788.7

申请日：2006-12-22

申请人： STMicroelectronics S.r.l.

发明人： Casarsa, Marco

IPC分类号： G01R31/3185

CPC分类号： G01R31/318541

公开(公告)号：EP1787136B1

公开(公告)日：2009-06-03

申请号：EP05703024.9

申请日：2005-02-22

申请人： NXP B.V.

发明人： Goel, Sandeep K.

IPC分类号： G01R31/3185

CPC分类号： G01R31/318536 ,  G01R31/318541

摘要： A wrapper architecture has a parent core A and a child core B. The parent core A comprises scan chains (70), wrapper input cells (71), wrapper output cells (74) and a parent TAM, PTAM [0:2]. Likewise, the child core comprises scan chains (76), wrapper input cells (75) and wrapper output cells (72), and is connected to a child TAM, CTAM [0:2]. Each wrapper input cell (75) and each wrapper output cell (72) of the child core is adapted to be connected to the parent TAM, PTAM, in addition to being connected to the child TAM, CTAM, thereby enabling the child core to be placed in the In-test and Ex-test modes at the same time, and allowing the parent and child cores to be tested in parallel.

公开(公告)号：EP1989562A1

公开(公告)日：2008-11-12

申请号：EP07757747.6

申请日：2007-03-01

申请人： QUALCOMM Incorporated

发明人： GARG, Manish ,  HAMDAN, Fadi Adel

IPC分类号： G01R31/3185 ,  G11C29/00 ,  H03K3/037

CPC分类号： G01R31/318541 ,  G01R31/318572 ,  G11C29/1201 ,  G11C29/32

摘要： A dual-path, multimode sequential storage element (SSE) (10) is described herein. In one example, the dual-path, multimode SSE comprises first (14) and second (12) sequential storage elements, a data input, a data output, and a selector mechanism (16). The first and second sequential storage elements (14, 12) each have an input and an output. The data input is coupled to the inputs of both sequential storage elements and is configured to accept data. The data output is coupled to the outputs of both sequential storage elements and is configured to output the data. The selector mechanism (16) is configured to select one of the sequential storage elements for passing the data from the data input to the data output. In one example, the first sequential storage element comprises a pulse-triggered storage element (14) and the second sequential storage element comprises a master-slave storage element (12).

公开(公告)号：EP1917535A2

公开(公告)日：2008-05-07

申请号：EP06795621.9

申请日：2006-08-09

申请人： NXP B.V.

发明人： NIEUWLAND, Andre, K. ,  GOEL, Sandeepkumar ,  MARINISSEN, Erik, J. ,  VERMEULEN, Hubertus, G., H. ,  VRANKEN, Hendrikus, P., E.

IPC分类号： G01R31/317

CPC分类号： G01R31/318541 ,  G01R31/31719

摘要： An integrated circuit (10) comprises a scan chain (14) with parallel inputs and outputs coupled to a functional circuit (12a-c). A scan chain modifying circuit (43, 47, 70a-c) is provided coupled to the scan chain (14). When testing is authorized the scan chain modifying circuit operates in a mode wherein a normal shift path is provided through the scan chain. When testing is not authorized the scan chain modifying circuit (43, 47, 70a-c) operates to effect spontaneous dynamic changes in the shift path, which dynamically vary the length of the shift path between external terminals of the integrated circuit while shifting takes place. In an embodiment the dynamical variations are controlled by a running key comparison. In other embodiments running key comparison is used to disable transfer through the scan chain and/or operation of functional circuits.

摘要翻译： 集成电路（10）包括具有耦合到功能电路（12a-c）的并行输入和输出的扫描链（14）。 扫描链修改电路（43,47,70a-c）被提供为耦合到扫描链（14）。 当测试被授权时，扫描链修改电路以其中通过扫描链提供正常移位路径的模式操作。 当测试未被授权时，扫描链修改电路（43,47,70a-c）操作以实现移位路径中的自发动态变化，其在移位发生时动态地改变集成电路的外部端子之间的移位路径的长度 。 在一个实施例中，动态变化由运行键比较来控制。 在其他实施例中，运行密钥比较被用于禁止通过扫描链的传输和/或功能电路的操作。

公开(公告)号：EP1873540A1

公开(公告)日：2008-01-02

申请号：EP07252569.4

申请日：2007-06-25

申请人： Silicon Image, Inc.

发明人： Sul, Chinsong

IPC分类号： G01R31/3185 ,  G01R31/319 ,  G06F11/27

CPC分类号： G01R31/318552 ,  G01R31/318541 ,  G01R31/318594 ,  G01R31/31922

摘要： Systems, structures and methods for generating a test clock for scan chains to implement scan-based testing of electronic circuits are disclosed. In one embodiment, a test clock control structure includes a programmable test clock controller. The programmable test clock controller includes a test clock generator for generating a configurable test clock. It also includes a scan layer interface to drive a scan chain portion with the configurable test clock, and a control layer interface configured to access control information for controlling the scan chain portion. In another embodiment, a method effectuates scan-based testing of circuits. The method includes performing at least one intra-domain test and performing at least one inter-domain test using implementing dynamic fault detection test patterns, which can include last-shift-launch test patterns and broadside test patterns.

摘要翻译： 系统，结构和方法，用于产生测试时钟为扫描链来实现电子电路的基于扫描的测试是游离缺失盘。 在一个，实施例的测试时钟控制结构包括可编程测试时钟控制器。 可编程测试时钟控制器包括用于产生可配置测试时钟的测试时钟发生器。 因此，它包括一扫描层接口，以驱动与所述可配置测试时钟的扫描链部分，并且被配置为访问控制信息用于控制在部分扫描链的控制层接口。 在另一个方法实施例effectuates电路的基于扫描测试。 该方法包括：执行至少一个域内测试以及使用实现动态故障检测测试图案，其可包括最后移发射测试模式和宽边测试图案的至少一个域间测试。

公开(公告)号：EP1367404B1

公开(公告)日：2007-08-29

申请号：EP03012093.5

申请日：2003-05-28

申请人： NEC Electronics Corporation

发明人： Kanba, Koji

IPC分类号： G01R31/3185 ,  G11C29/00

CPC分类号： G11C29/025 ,  G01R31/318541 ,  G11C29/02 ,  G11C2029/3202

公开(公告)号：EP0804468B1

公开(公告)日：2007-04-25

申请号：EP95919592.6

申请日：1995-06-08

申请人： DeveloGen Israel Ltd. ,  YISSUM RESEARCH DEVELOPMENT COMPANY OF THE HEBREW UNIVERSITY OF JERUSALEM

发明人： GILON, Chaim ,  EREN, Doron ,  ZELTSER, Irina ,  SERI-LEVY, Alon ,  BITAN, Gal ,  MULLER, Dan

IPC分类号： C07K7/02 ,  C07K14/655 ,  C07K7/18 ,  C07C271/22

CPC分类号： C07K14/001 ,  A61K38/00 ,  C07C271/22 ,  C07K7/02 ,  C07K7/18 ,  C07K7/56 ,  C07K14/6555 ,  G01R31/318541 ,  Y02P20/55

摘要： Novel backbone cyclized peptide analogs are formed by means of bridging groups attached via the alpha nitrogens of amino acid derivatives to provide novel non-peptidic linkages. Novel building units disclosed are N /( omega -functionalized) amino acids constructed to include a spacer and a terminal functional group. One or more of these N ( omega -functionalized) amino acids are incorporated into a peptide sequence, preferably during solid phase peptide synthesis. The reactive terminal functional groups are protected by specific protecting groups that can be selectively removed to effect either backbone-to-backbone or backbone-to-side chain cyclizations. The invention is exemplified by backbone cyclized bradykinin antagonists having biological activity. Further embodiments of the invention are somatostatin analogs having one or two ring structures involving backbone cyclization.

公开(公告)号：EP1728083A2

公开(公告)日：2006-12-06

申请号：EP05703033.0

申请日：2005-02-24

申请人： Koninklijke Philips Electronics N.V.

发明人： BINK, Adrianus, J. ,  DE CLERCQ, Mark, N., O.

IPC分类号： G01R31/28

CPC分类号： G06F11/2236 ,  G01R31/31723 ,  G01R31/318541

摘要： An electronic circuit is provided that comprises first and second combinational logic blocks and a latch positioned between the combinational logic blocks; wherein the electronic circuit is adapted to operate in a normal mode in which the latch is opened and closed in response to an enable signal, and a test mode in which the latch is held open.

公开(公告)号：EP1637894A3

公开(公告)日：2006-06-07

申请号：EP05077021.3

申请日：2001-08-07

申请人： Agere Systems Guardian Corporation

发明人： Goldovsky, Alexander

IPC分类号： G01R31/3185

CPC分类号： G01R31/318541 ,  G01R31/318538 ,  G01R31/318594

摘要： An integrated circuit includes a semiconductor die having a plurality of input/output pads. A plurality of boundary scan cells, one corresponding to each input/output pad, implements boundary scan functions associated with respective input/output pads. Each of the boundary scan cells includes a TDI input and a TDO output. The boundary scan cells are structured as a shift register to shift data from one boundary scan cell in a direction unilaterally to an adjacent boundary scan cell. A first boundary scan cell is the first boundary scan cell of the plurality of boundary scan cells to receive data. A last boundary scan cell is the last boundary scan cell of the plurality of boundary scan cells to receive data. An endless control conductor forms a loop proximate the plurality of boundary scan cells. The endless control conductor is coupled to each of the plurality of boundary scan cells to provide a test clock signal thereto. At least one other control conductor extends around the semiconductor die proximate the plurality of boundary scan cells. The at least one other control conductor is discontinuous between the first and last boundary scan cells. The invention can also be implemented at the system level.

摘要翻译： 集成电路包括具有多个输入/输出焊盘的半导体管芯。 对应于每个输入/输出焊盘的多个边界扫描单元实现与各个输入/输出焊盘相关联的边界扫描功能。 每个边界扫描单元包括TDI输入和TDO输出。 边界扫描单元被构造为移位寄存器，用于将单边方向上的一个边界扫描单元的数据移动到相邻的边界扫描单元。 第一边界扫描单元是用于接收数据的多个边界扫描单元的第一边界扫描单元。 最后一个边界扫描单元是用于接收数据的多个边界扫描单元的最后边界扫描单元。 无限制的控制导体形成靠近多个边界扫描单元的环路。 无限制控制导体耦合到多个边界扫描单元中的每一个，以向其提供测试时钟信号。 至少一个其它控制导体围绕半导体管芯在多个边界扫描单元附近延伸。 所述至少一个其它控制导体在所述第一和最后边界扫描单元之间是不连续的。 本发明也可以在系统级实现。