摘要:
An analog sample-and-hold switch has parallel branches extending from an input node to an output node connected to a hold capacitor, each branch having a PMOS signal switch FET in series with a PMOS dummy FET. A sample clock controls on-off switching of the PMOS signal switch FETs, and an inverse of the sample clock controls a complementary on-off switching of the PMOS dummy FETs. A bias sequencer circuit biases the PMOS signal switch FETs and biases the PMOS dummy FETs, in a complementary manner, synchronous with their respective on-off states. The on-off switching of the PMOS dummy FETs injects charge cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs.
摘要:
The power supply unit has a sample-and-hold circuit that samples a voltage supplied from a power source to a load according to a sample timing signal and holds the voltage as an output set value for the DC/DC converter. The unit supplies a load with an output from the DC/DC converter controlled so that an output voltage of power source (22) becomes an output set value of the DC/DC converter when the voltage of power source (22) drops. Since a voltage corresponding to the voltage of the power source before the voltage drop is set to the output set value of the DC/DC converter, a stable power supply unit is obtained in which the difference is always small between the voltage of the power source in normal times and the output voltage from the DC/DC converter when the voltage of the power source temporarily fluctuates.