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    NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES
    13.
    发明公开
    NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES 审中-公开
    具有多细胞基质NAND闪存

    公开(公告)号：EP2238597A1

    公开(公告)日：2010-10-13

    申请号：EP08869440.1

    申请日：2008-12-23

    申请人： MOSAID Technologies Incorporated

    发明人： KIM, Jin-Ki

    IPC分类号： G11C16/14 ,  G11C16/24

    CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11524

    摘要： A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.

    DUAL FUNCTION COMPATIBLE NON-VOLATILE MEMORY DEVICE
    14.
    发明公开
    DUAL FUNCTION COMPATIBLE NON-VOLATILE MEMORY DEVICE 审中-公开
    DOUBLE功能相兼容的非易失性存储器设备

    公开(公告)号：EP2223302A1

    公开(公告)日：2010-09-01

    申请号：EP08864264.0

    申请日：2008-12-11

    申请人： MOSAID Technologies Incorporated

    发明人： KIM, Jin-Ki

    IPC分类号： G11C16/06

    CPC分类号： G11C16/06 ,  G11C5/14 ,  G11C5/143 ,  G11C7/20 ,  G11C16/20

    摘要： A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.

    INDEPENDENT LINK AND BANK SELECTION
    15.
    发明公开
    INDEPENDENT LINK AND BANK SELECTION 审中-公开
    独立的银行连接和选择

    公开(公告)号：EP2126918A1

    公开(公告)日：2009-12-02

    申请号：EP07855602.4

    申请日：2007-12-21

    申请人： Mosaid Technologies Incorporated

    发明人： PYEON, Hong, Beom ,  OH, HakJune ,  KIM, Jin-Ki

    IPC分类号： G11C8/12 ,  G11C29/26

    CPC分类号： G06F13/4022 ,  G11C7/1048 ,  G11C7/18 ,  G11C11/408

    摘要： Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.

    NON- VOLATILE SEMICONDUCTOR MEMORY WITH PAGE ERASE
    18.
    发明公开
    NON- VOLATILE SEMICONDUCTOR MEMORY WITH PAGE ERASE 审中-公开
    同方消光不挥发半导体存储器

    公开(公告)号：EP1999755A1

    公开(公告)日：2008-12-10

    申请号：EP07719413.2

    申请日：2007-03-26

    申请人： Mosaid Technologies Incorporated

    发明人： KIM, Jin-Ki

    IPC分类号： G11C7/20 ,  G11C11/40 ,  G11C8/08 ,  G11C8/12

    CPC分类号： G11C16/04 ,  G11C7/20 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/344 ,  G11C16/3445

    摘要： In a nonvolatile memory, less than a full block may be erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A substrate voltage is applied to the substrate of the selected block. A common select voltage may be applied to each selected wordline and the common unselect voltage may be applied to each unselected wordline. Select and unselect voltages may be applied to any of the wordlines of a select block. A page erase verify operation may be applied to a block having plural erased pages and plural nonerased pages.

    DAISY CHAIN CASCADING DEVICES
    20.
    发明公开
    DAISY CHAIN CASCADING DEVICES 有权
    DAISY链式连接器

    公开(公告)号：EP1929480A1

    公开(公告)日：2008-06-11

    申请号：EP06790771.7

    申请日：2006-09-29

    申请人： Mosaid Technologies Incorporated

    发明人： PYEON, Hong, Beom ,  KIM, Jin-Ki ,  OH, HakJune

    IPC分类号： G11C7/10 ,  G11C11/4197 ,  G11C16/06

    CPC分类号： G11C7/10 ,  G06F12/0623 ,  G06F13/4247 ,  G06F13/4256 ,  G11C5/066 ,  G11C16/06

    摘要： A technique for serially coupling devices in a daisy chain cascading arrangement. Devices are coupled in a daisy chain cascade arrangement such that outputs of a first device are coupled to inputs of a second device later in the daisy chain to accommodate the transfer of information, such as data, address and command information, and control signals to the second device from the first device. The devices coupled in the daisy chain comprise a serial input (SI) and a serial output (SO). Information is input to a device via the SI. The information is output from the device via the SO. The SO of an earlier device in the daisy chain cascade is coupled to the SI of a device later in the daisy chain cascade. Information input to the earlier device via the device's SI is passed through the device and output from the device via the device's SO. The information is then transferred to the later device's SI via the connection from the earlier device's SO and the later device's SI.

    摘要翻译： 串联耦合设备的技术，采用菊花链级联布置。 设备以菊花链级联布置耦合，使得第一设备的输出在菊花链中稍后耦合到第二设备的输入以适应信息（诸如数据，地址和命令信息以及控制信号）向 来自第一设备的第二设备。 耦合在菊花链中的器件包括串行输入（SI）和串行输出（SO）。 信息通过SI输入到设备。 信息通过SO从设备输出。 菊花链级联中的较早器件的SO在菊花链级联中稍后与器件的SI相耦合。 通过设备的SI输入到较早设备的信息通过设备并通过设备的SO从设备输出。 然后通过来自早期设备的SO和后面的设备的SI的连接将信息传送到更晚的设备的SI。