利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

25 条记录 (耗时 0.013 秒)

    Computer memory
    13.
    发明公开
    Computer memory 失效
    Computerspeicher。

    公开(公告)号：EP0109298A2

    公开(公告)日：1984-05-23

    申请号：EP83306931.3

    申请日：1983-11-14

    申请人： DATA GENERAL CORPORATION

    发明人： Ziegler, Michael ,  Marshall, Peter G. ,  Whipple, David L.

    IPC分类号： G06F13/00 ,  G11C11/40

    CPC分类号： G06F12/0607 ,  G11C11/407

    摘要： Selection logic (1) responds to 7 out of 22 address bits on a bus (19) to select the module by providing a signal SETRAS, delayed by a signal PRECHG if the same row is address twice in succession. SETRAS generates a row address strobe RAS, a recognition signal ANYRAS and, after a delay (11), a column address signal CAS 16 address bits held in a latch (3) are multiplexed 8 bits at a time a multiplexer (4) and, in synchronism with RAS and CAS select locations in even and odd memory arrays (16 and 17). Two more address bits and selection logic (20) select between four planes in each array. The memory controller responds to the recognition signal ANYRAS to provide an output strobe DOUTSTB - DOUTLTCH to enter both read out words into latches (7, 8). Either (or both in sequence) of further signals from the controller DRVDOUTO, cause one or both words to be read out in sequence to the data bus (18).

    摘要翻译： 选择逻辑（1）响应总线（19）上的22个地址位中的7个，通过提供信号SETRAS来选择模块，如果相同的行是连续两次是相同的行，则由信号PRECHG延迟。 SETRAS产生行地址选通RAS，识别信号ANYRAS，并且在延迟（11）之后，保持在锁存器（3）中的列地址信号CAS 16地址位被多路复用器8复用8位， 与RAS和CAS同步选择偶数和奇数存储器阵列（16和17）中的位置。 两个地址位和选择逻辑（20）在每个阵列中的四个平面之间进行选择。 存储器控制器响应识别信号ANYRAS以提供输出选通DOUTSTB-DOUTLTCH，以将两个读出的字输入到锁存器（7,8）中。 来自控制器DRVDOUTO，1的进一步信号（或者顺序地）两者之一（或两者都顺序地）使得一个或两个字被依次读出到数据总线（18）。

    System for driving a dynamic random access memory device
    15.
    发明公开
    System for driving a dynamic random access memory device 失效
    对于随机存取存储器控制系统。

    公开(公告)号：EP0068893A2

    公开(公告)日：1983-01-05

    申请号：EP82303413.7

    申请日：1982-06-29

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro ,  Nakano, Tomio

    IPC分类号： G11C11/24

    CPC分类号： G11C11/406 ,  G11C11/407

    摘要： In a dynamic random access memory device, the memory cells (1-1, 1-2), sense amplifiers (2), word drivers (3-1, 3-2), and the like are divided into a plurality of blocks (BK 1 , BK 2 ). During the access mode, only one of the blocks in which a desired row exists is driven while, during the refresh mode, all of the blocks are driven.

    Memory device
    16.
    发明公开
    Memory device 失效
    存储设备

    公开(公告)号：EP0017228A1

    公开(公告)日：1980-10-15

    申请号：EP80101776.5

    申请日：1980-04-03

    申请人： NEC CORPORATION

    发明人： Nagami, Akira

    IPC分类号： G11C11/24 ,  G11C8/00

    CPC分类号： G11C11/407 ,  G11C8/16

    摘要： In a dynamic random access memory including means for inputting a row strobe signal and means for inputting a column strobe signal, and having the functions of incorporating a row address input in response to the row strobe signal and incorporating a column address input in response to the column strobe signal; the improvement comprises a first insulated gate field effect transistor having drain coupled to a first junction point, gate receiving the column strobe signal and source supplied with a first power supply, means for charging the first junction point within a period of active level of the row strobe signal, a second insulated gate field effect transistor having a drain coupled to the first junction point, gate coupled to a second junction point and source supplied with the first power supply terminal, means for precharghing the second junction point within a period of absence of the row strobe signal, and a third insulated gate field effect transistor having drain coupled to the second junction point, the gate supplied with the column strobe signal and source supplied with the first power supply. After completion of a desired operation with respect to a selected memory cell, the row strobe signal is made at its inactive level to be reset while the column strobe signal is at its active level. Then, after a necessary reset period when the row strobe signal is made active a change from inactive level to active level of the first junction point is suppressed thereby to inhibit active operation based on the column strobe signal.

    摘要翻译： 在包括用于输入行选通信号的装置和用于输入列选通信号的装置的动态随机存取存储器中，并且具有响应行选通信号并入行地址输入和响应 列选通信号; 该改进包括具有耦合到第一结点的漏极的第一绝缘栅极场效应晶体管，接收列选通信号的栅极和提供有第一电源的源极，用于在行的有效电平的时段内对第一结点充电的装置 选通信号;第二绝缘栅极场效应晶体管，其具有耦合到所述第一结点的漏极，栅极耦合到第二结点和提供有所述第一电源端子的源极，用于在不存在 行选通信号和第三绝缘栅极场效应晶体管，漏极耦合到第二结点，栅极被提供有列选通信号，并且源极被提供有第一电源。 在完成对所选存储单元的期望操作之后，行选通信号处于其无效电平，以在列选通信号处于其有效电平时被复位。 然后，在行选通信号被激活的必要的复位周期之后，抑制第一节点的无效电平到有效电平的改变，由此基于列选通信号禁止激活操作。

    CMOS IMAGE SENSOR WITH NOISE CANCELLATION
    17.
    发明公开
    CMOS IMAGE SENSOR WITH NOISE CANCELLATION 审中-公开
    噪音消除CMOS图像传感器

    公开(公告)号：EP1452015A1

    公开(公告)日：2004-09-01

    申请号：EP02782274.1

    申请日：2002-11-06

    申请人： Candela Microsystems

    发明人： TAY, Hiok, Nam

    IPC分类号： H04N5/335 ,  H04N5/217

    CPC分类号： G11C11/407 ,  H01L27/14643 ,  H04N1/32358 ,  H04N1/32475 ,  H04N1/32491 ,  H04N1/40 ,  H04N5/3575 ,  H04N5/363 ,  H04N5/378 ,  H04N9/045 ,  H04N9/64 ,  H04N9/642 ,  H04N2201/0081 ,  H04N2201/3292

    摘要： An image sensor (10) that has one or more pixels within a pixel array (12). The pixel array may be coupled to a control circuit (20) and one or more subtraction circuits (56). The control circuit may cause each pixel to provide a first reference output signal and a reset output signal. The control circuit may then cause each pixel to provide a light response output signal and a second reference output signal. The light response output signal corresponds to the image that is to be captured by the sensor. The subtraction circuit may provide a difference between the reset output signal and the first reference output signal to create a noise signal that is stored in memory. The subtraction circuit may also provide a difference between the second reference output signal and the light response output signal to create a normalized light response output signal. The noise signal may then be subtracted from the normalized light response output signal to generate the output data of the sensor. The second reference output signal is the same as the first reference output signal so that the process in essence subtracts the reset noise from the light response signal.

    Semiconductor memory device capable of setting the magnitude of substrate voltage in accordance with the mode
    19.
    发明公开
    Semiconductor memory device capable of setting the magnitude of substrate voltage in accordance with the mode 失效
    要设置半导体存储器装置，其能够在衬底电压的大小依赖于条件

    公开(公告)号：EP0790618A1

    公开(公告)日：1997-08-20

    申请号：EP96114904.4

    申请日：1996-09-17

    申请人： MITSUBISHI DENKI KABUSHIKI KAISHA

    发明人： Nakai, Jun

    IPC分类号： G11C5/14 ,  G11C11/407

    CPC分类号： G11C11/407 ,  G11C5/14

    摘要： A DRAM includes a substrate voltage generation unit (35) for generating a substrate voltage (Vbb) having a negative value to be applied to a first node (N1). The substrate voltage generation unit (35) includes a detecting circuit (53). The detecting circuit (53) includes a first PMOS transistor (197) provided in series between a second node with a ground potential and a third node (A) and a second PMOS transistor (61), and further includes a third PMOS transistor (199) provided in parallel to the first PMOS transistor (197). The first and second PMOS transistors (197, 61) have the gates connected to the third node (A), and the third PMOS transistor (199) has a gate receiving a signal (ZBBU). The detecting circuit (53) is provided between the second node with the ground voltage and the first node (N1), and further includes an NMOS transistor (71) having a gate connected to the third node (A). The third PMOS transistor (199) receives the signal (ZBBU) of the "L" level in the self refresh mode and the signal (ZBBU) of the "H" level in the normal mode. As a result, the clamp level of the substrate voltage (Vbb) is greater in the self refresh mode than in the normal mode. More specially, the NMOS transistor (71) is turned on with the greater substrate voltage (Vbb) in the self refresh mode than the normal mode, so that the substrate voltage (Vbb) is increased and the capability of pause refresh is improved. Consequently, the interval of internal /RAS can be increased and power consumption can be reduced in the self refresh mode.

    摘要翻译： 甲DRAM包括用于生成具有要被施加到第一节点（N1）负值的基片电压（VBB）一个基片电压产生单元（35）。 基板电压生成部（35）包括一个检测电路（53）。 检测电路（53）包括：第一PMOS晶体管（197）串联地电势和第三结点（A）和第二PMOS第二节点之间提供晶体管（61），并且还包括第三PMOS晶体管（199 ）提供（在平行于第一PMOS晶体管197）。 所述第一和第二PMOS晶体管（197，61），具有连接到第三结点（A）的栅极，和所述第三PMOS晶体管（199）的栅极接收的信号（ZBBU）。 与接地电压的第二节点和第一节点（N1）之间，设置上述检测电路（53），并且进一步包括在具有连接至所述第三结点（A）的栅NMOS晶体管（71）。 第三PMOS晶体管（199）接收在自刷新模式和正常模式中的“H”电平的信号（ZBBU）中的“L”电平的信号（ZBBU）。 其结果是，基板电压（V BB）的钳位电平大于在正常模式下更高的在自刷新模式。 更特别地，NMOS晶体管（71）与在自刷新模式中比正常模式下的更大的衬底电压（V BB）导通，所以做了衬底电压（V BB）增大和断裂刷新能力得到改善。 因此，内/ RAS的时间间隔可以增加，并且可以在自刷新模式时可以降低耗电量。