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78 条记录 (耗时 0.017 秒)

    Method, circuit and systems for erasing one or more non-volatile memory cells
    34.
    发明公开
    Method, circuit and systems for erasing one or more non-volatile memory cells 审中-公开
    的方法，电路和系统用于擦除一个或多个非易失性存储器单元

    公开(公告)号：EP1684307A1

    公开(公告)日：2006-07-26

    申请号：EP06100524.5

    申请日：2006-01-18

    申请人： Saifun Semiconductors Ltd.

    发明人： Shappir, Assaf ,  Eisen, Shai

    IPC分类号： G11C16/14

    CPC分类号： G11C16/10 ,  G06F12/1408 ,  G11C11/5635 ,  G11C16/0475 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/349 ,  G11C2216/18

    摘要： The present invention is a method, circuit and system for erasing one or more non-volatile memory ("NVM") cells in an NVM array or array segment, According to some embodiments of the present invention, one or more erase pulse parameters may be associated with each of a number of array segments within an NVM array. Separate erase pulse parameters may be associated with anywhere from one to all of the array segments within an NVM array. According to some embodiments of the present invention, a characteristic of an erase pulse (e.g. pulse amplitude, pulse duration, etc.) applied to one or more MVM cells within art array segment may be at least partially on one or more erase pulse parameters associated with the given array segment.

    摘要翻译： 本发明是用于擦除一个或多个非易失性存储器（“NVM”）细胞在NVM阵列或阵列段，。根据本发明的一些实施例的方法，电路和系统中，一个或多个擦除脉冲参数可以是 在NVM阵列内每个若干阵列段中的相关联。 单独的擦除脉冲参数可以与在NVM阵列内从一个到所有阵列段的任何位置相关联。 。根据本发明，一个擦除脉冲的特征的一些实施例中（例如脉冲幅值，脉冲持续时间等）适用于本领域阵列段内的一个或多个MVM细胞可以是在一个或多个擦除脉冲参数至少部分地相关联的 与给定阵列段。

    A non-volatile memory device controlled by a micro-controller
    36.
    发明公开
    A non-volatile memory device controlled by a micro-controller 审中-公开
    。。。。。。。。。。。。。。

    公开(公告)号：EP1632952A2

    公开(公告)日：2006-03-08

    申请号：EP05254988.8

    申请日：2005-08-11

    申请人： Saifun Semiconductors Ltd.

    发明人： Edan, Mori ,  Sofer, Yair ,  Grossgold, Meir ,  Eliyahu, Ron

    IPC分类号： G11C16/20

    CPC分类号： G11C16/20

    摘要： A system and a method for operating a non-volatile memory (NVM) device including a micro-controller adapted to control peripheral circuitry associated with an NVM array. The method includes providing at least one operation command to the micro-controller of the NVM device and applying operating signals to peripheral circuitry of the NVM device to operate the NVM array based on at least one operation command. The system includes: a NVM device (20) with a NVM array (28) adapted to store data and commands, peripheral circuitry (P 1 ...P n ) adapted to operate the NVM array and a micro-controller (24) adapted to control the peripheral circuitry; and an external device to provide at least one command to the micro-controller of the NVM device.

    摘要翻译： 一种用于操作非易失性存储器（NVM）装置的系统和方法，包括适于控制与NVM阵列相关联的外围电路的微控制器。 该方法包括向NVM设备的微控制器提供至少一个操作命令，并且基于至少一个操作命令向NVM设备的外围电路施加操作信号以操作NVM阵列。 该系统包括：具有适于存储数据和命令的NVM阵列（28）的NVM设备（20），适于操作NVM阵列的外围电路（P 1 ... P n）和适于 控制外围电路; 以及向NVM设备的微控制器提供至少一个命令的外部设备。

    PROGRAMMING OF NONVOLATILE MEMORY CELLS
    37.
    发明公开
    PROGRAMMING OF NONVOLATILE MEMORY CELLS 审中-公开
    PROGRAMMIERUNG NICHTFL CHTIGER SPEICHERZELLEN

    公开(公告)号：EP1287527A4

    公开(公告)日：2006-02-08

    申请号：EP01929943

    申请日：2001-05-03

    申请人： SAIFUN SEMICONDUCTORS LTD

    发明人： BLOOM ILAN ,  EITAN BOAZ ,  COHEN ZEEV ,  FINZI DAVID ,  MAAYAN EDUARDO

    IPC分类号： G11C5/00 ,  G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C16/3481 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/3454 ,  G11C16/3468

    摘要： A method for programming an NROM cell which includes the steps of applying a drain (VD), a source (VS) and a gate voltage (VG) to the cell and verifying a programmed or a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and maintaining the gate voltage at a constant level during at least a part of the step of increasing. The steps of applying, verifying, increasing and maintaining are repeated until the cell reaches the programmed state.

    摘要翻译： 一种用于对NROM单元进行编程的方法，其包括向单元施加漏极（VD），源极（VS）和栅极电压（VG）并验证单元的编程或未编程状态的步骤。 如果单元处于未编程状态，则该方法包括在增加步骤的至少一部分期间增加漏极电压并将栅极电压保持在恒定电平的步骤。 重复施加，验证，增加和维护的步骤，直到细胞达到编程状态。

    A SYMMETRIC SEGMENTED MEMORY ARRAY ARCHITECTURE
    38.
    发明公开
    A SYMMETRIC SEGMENTED MEMORY ARRAY ARCHITECTURE 审中-公开
    对称不间断SPEICHERBLOCKARCHITEKTUR

    公开(公告)号：EP1218888A4

    公开(公告)日：2005-04-06

    申请号：EP98959125

    申请日：1998-12-10

    申请人： SAIFUN SEMICONDUCTORS LTD

    发明人： EITAN BOAZ

    IPC分类号： H01L21/8247 ,  G11C7/18 ,  G11C11/56 ,  G11C16/04 ,  H01L27/02 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C17/00 ,  G11C5/06 ,  G11C7/00 ,  G11C11/40 ,  H01L27/105

    CPC分类号： H01L27/115 ,  G11C7/18 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/24 ,  H01L27/0207

    摘要： A symmetric memory array includes a multiplicity of repeating segments (A, B, C, D) formed into rows and columns. Each segment includes a cell area formed of four segmented cell bit lines (i,i+1), an even select area and an odd select area. The even select area is located at one end of the cell area and includes a segmented even contact bit line and two select transistors (Ei,Ei+1) connecting the even contact bit line with the even cell bit lines of the segment. The odd select area is located at the opposite end of the cell area and includes a segmented odd contact bit line and two select transistors (Oi, Oi+1) connecting the odd contact bit line with the odd cell bit lines of the segment. The array additionally includes one even contact connected to the even contact bit lines of two neighboring even select areas, one odd contact connected to the odd contact bit lines of two neighboring odd select areas and alternating even and odd metal lines connecting to the even and odd contacts, respectively.

    摘要翻译： 对称存储器阵列包括形成行和列的多个重复段。 每个段包括由四个分段的单元位线，偶数选择区和奇数选择区构成的单元区。 均匀选择区域位于单元区域的一端，并且包括分段的偶数位线以及将偶数位线与该段的偶数单元位线连接的两个选择晶体管。 奇数选择区域位于单元区域的相对端，并且包括分段的奇数接触位线和将奇数接触位线与该段的奇数单元位线连接的两个选择晶体管。 该阵列还包括连接到两个相邻偶数选择区域的偶数位线的一个偶数触点，连接到两个相邻奇数选择区域的奇数接触位线的一个奇数触点和连接到偶数和奇数的交替偶数和奇数金属线 联系人。

    Alternating application of pulses on two sides of a cell
    39.
    发明公开
    Alternating application of pulses on two sides of a cell 审中-公开
    Wechselweise Anlegen von Pulsen一个zwei Seiten einer Zelle

    公开(公告)号：EP1463062A1

    公开(公告)日：2004-09-29

    申请号：EP04007003.9

    申请日：2004-03-24

    申请人： Saifun Semiconductors Ltd.

    发明人： Shappir, Assaf

    IPC分类号： G11C16/04 ,  G11C16/34

    CPC分类号： G11C16/3459 ,  G11C16/3454

    摘要： A method for operating on bits of a memory cell, the method comprising providing a memory cell that has two separated and separately chargeable areas on first and second sides of the cell, each chargeable area defining one bit, applying an injection pulse and a verify pulse on the first side of the cell, and before the first side of the cell has reached a verify level, applying an injection pulse and a verify pulse on the second side of the cell.

    摘要翻译： 一种用于对存储器单元的位进行操作的方法，所述方法包括提供存储单元，所述存储单元在所述单元的第一和第二侧上具有两个分开且可分开的可充电区域，每个可充电区域定义一位，施加注入脉冲和验证脉冲 在单元的第一侧，并且在单元的第一侧达到验证电平之前，在单元的第二侧上施加注入脉冲和验证脉冲。

    Programming and erasing methods for an NROM array
    40.
    发明公开
    Programming and erasing methods for an NROM array 审中-公开
    编程和擦除方法的NROM存储

    公开(公告)号：EP1227501A3

    公开(公告)日：2003-07-30

    申请号：EP01309290.3

    申请日：2001-11-01

    申请人： Saifun Semiconductors Ltd.

    发明人： Avni, Dror ,  Eitan, Boaz

    IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C16/14

    CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/14 ,  G11C16/28 ,  G11C16/3468 ,  G11C16/3481

    摘要： A method for programming and erasing a memory array includes the step of adapting programming or erase pulses to the current state of the memory array. In one embodiment, the step of adapting includes the steps of determining the voltage level of the programming pulse used to program a fast bit of the memory array and setting an initial programming level of the memory array to a level in the general vicinity of the programming level of the fast bit. For erasure, the method includes the steps of determining erase conditions of the erase pulse used to erase a slowly erasing bit of said memory array and setting initial erase conditions of said memory array to the general vicinity of said erase conditions of said slowly erasing bit. In another embodiment of the array, the step of adapting includes the steps of measuring the current threshold level of a bit to within a given range and selecting an incremental voltage level of a next programming or erase pulse for the bit in accordance with the measured current threshold level.