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    Method of making an integrated vertical bipolar transistor
    32.
    发明公开
    Method of making an integrated vertical bipolar transistor 审中-公开
    Verfahren zur Herstellung eine integrierten，vertikalen Bipolartransistors

    公开(公告)号：EP0961316A3

    公开(公告)日：2003-06-25

    申请号：EP99110147.8

    申请日：1999-05-25

    申请人： NEC Electronics Corporation

    发明人： Yoshida, Hiroshi, c/o NEC Corporation

    IPC分类号： H01L21/331 ,  H01L21/8228 ,  H01L21/8249

    CPC分类号： H01L21/8249 ,  H01L21/82285

    摘要： There is provided a method of manufacturing a semiconductor device which can use commonly a part of a step of forming a PNP transistor with a step of forming an NPN transistor. In an area separated by a side separation region (5) of PNP formed by doping N-type impurities simultaneously with the formation of the collector region (4) of NPN, an N-type bottom separation region (8) of PNP, a collector region (9) and a base region (10) are formed by using the same mask. Trenches (18, 17) extending to the collector regions (9, 4) are formed by an over-etching treatment carried out when the emitter electrodes (16, 15) of PNP and NPN are subjected to a patterning treatment, and N-type impurities are doped through the trench (17) simultaneously with the formation of an external base region (20) of PNP, thereby forming a collector drawing region (21) of NPN. Further, P-type impurities are doped through the trench (18) simultaneously with the formation of an external base region (19) of NPN, thereby forming a collector drawing region (22) of PNP.

    摘要翻译： 提供一种半导体器件的制造方法，该半导体器件可以在形成NPN晶体管的步骤中共同地使用形成PNP晶体管的步骤的一部分。 在由形成NPN的集电极区域（4）同时掺杂N型杂质的PNP的侧分离区域（5）分离的区域中，PNP的N型底部分离区域（8），集电体 通过使用相同的掩模形成区域（9）和基底区域（10）。 通过对PNP和NPN的发射电极（16,15）进行图案化处理时进行的过蚀刻处理形成延伸到集电体区域（9,4）的沟槽（18,17），并且N型 杂质通过沟槽（17）掺杂，同时形成PNP的外部基极区域（20），从而形成NPN的集电极绘图区域（21）。 此外，P型杂质通过沟槽（18）掺杂，同时形成NPN的外部基极区域（19），从而形成PNP的集电极绘图区域（22）。

    Semiconductor device including a plurality of bipolar transistors
    34.
    发明公开
    Semiconductor device including a plurality of bipolar transistors 审中-公开
    Halbleiterbauelement mit einer Vielzahl von Bipolartransistoren

    公开(公告)号：EP0967642A1

    公开(公告)日：1999-12-29

    申请号：EP99304089.8

    申请日：1999-05-26

    申请人： Mitel Semiconductor Limited

    发明人： Osborne, Peter Hugh ,  Wilson, Martin Clive

    IPC分类号： H01L21/8222 ,  H01L21/8228 ,  H01L27/082

    CPC分类号： H01L27/0826 ,  H01L21/8228

    摘要： A number of npn and pnp bipolar transistors are formed in a single chip of silicon, so that some of the transistors have a greater frequency response than others The higher frequency transistors have their emitters (3) located closer to the collectors (1), by positioning a collector (1), or emitter (3), of a transistor in a recessed portion of the surface of the chip. The recess is formed in an accurate and controlled manner by locally oxidising the silicon surface, and subsequently removing the oxide to leave the recess.

    摘要翻译： 多个npn和pnp双极晶体管形成在单芯片硅中，使得一些晶体管具有比其他晶体管更大的频率响应。较高频率晶体管的发射极（3）位于更靠近集电极（1）的位置，由 将晶体管的集电极（1）或发射极（3）定位在芯片表面的凹陷部分中。 通过局部氧化硅表面，并且随后除去氧化物离开凹槽，以精确和可控的方式形成凹部。

    Process for doping two levels of a double poly bipolar transistor after formation of second poly layer
    37.
    发明公开
    Process for doping two levels of a double poly bipolar transistor after formation of second poly layer 失效
    过程用于双聚双极型晶体管的两个平面的掺杂

    公开(公告)号：EP0732746A2

    公开(公告)日：1996-09-18

    申请号：EP96301722.3

    申请日：1996-03-13

    申请人： HARRIS CORPORATION

    发明人： Beasom, James D.

    IPC分类号： H01L27/082 ,  H01L21/8228

    CPC分类号： H01L27/0826 ,  H01L21/8228 ,  H01L27/082

    摘要： A reduced mask set, implant complexity process for manufacturing a (high frequency application) complementary bipolar transistor structure uses the fast lateral diffusion characteristic of a layer of material, that is at least an order of magnitude higher for emitter dopants than in single crystal semiconductor material. Separate base and emitter poly layers are formed undoped. Then, the emitter poly of one device and the edges of the base poly of the other device are exposed through a dopant mask and simultaneously doped. The emitter dopant goes directly into the surface of the emitter poly where it lies over and is in contact with the base. The base contact dopant goes into the edges of the base poly, including the layer of material having the high diffusion coefficient, rapidly diffuses laterally throughout that layer, and then diffuses down into the collector material (e.g. island) surface, to form the extrinsic base. A second mask is patterned to expose the emitter of the second device and the edges of the base poly of the first device and subsequentally doped.

    摘要翻译： 减小的掩模组，一种用于制造（高频应用）互补双极晶体管结构使用的材料的一个层的几乎横向扩散特性注入复杂的过程，的确是至少一个比在单晶半导体材料的大小为发射极的掺杂剂更高的顺序 ， 单独的基极和发射极多晶硅层未掺杂形成。 然后，一个设备的发射极多晶硅和其他装置的基聚边缘通过掺杂剂掩模进行曝光，并同时掺杂。 发射掺杂剂直接进入发射极多晶硅的表面，其中它位于其上方并与底座接触。 基极接触掺杂物进入基聚的边缘上，包括具有高扩散系数的材料的层，快速扩散尾盘反弹整个做层，然后扩散向下进入收集器的材料（例如冰岛）表面，以形成所述非本征基极 ， 第二掩模被图案化，以暴露所述第二装置的所述发射极和所述第一设备和subsequentally掺杂的基聚的边缘。