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78 条记录 (耗时 0.014 秒)

    Method and circuit for minimizing the charging effect during manufacture of semiconductor devices
    42.
    发明公开
    Method and circuit for minimizing the charging effect during manufacture of semiconductor devices 审中-公开
    方法和电路用于半导体器件的制造过程中减少电荷的效应

    公开(公告)号：EP1061580A3

    公开(公告)日：2001-05-30

    申请号：EP00305161.2

    申请日：2000-06-19

    申请人： Saifun Semiconductors Ltd.

    发明人： Eitan, Boaz ,  Bloom, Ilan

    IPC分类号： H01L27/02

    CPC分类号： H01L27/0266 ,  H01L21/3065 ,  H01L21/31116 ,  H01L27/0251

    摘要： A protection device which is active during the manufacturing process of a semiconductor chip includes a protection transistor (52) and an antenna (55). The protection transistor is connected between a metal line (40) having devices to be protected electrically connected thereto and a ground supply (41), where the metal line is connected to devices (50) to be protected. The antenna is formed of the same metal layer as the metal line and controls the operation of the protection transistor during the manufacturing process. The antenna (55) is connected to a gate (G) of the protection transistor. Optionally, there is a metal ring (112, Fig. 7) around the antenna which is connected to a drain (D) of the protection transistor via the same metal layer as the metal line. During normal operation of the chip, the protection transistor is either active for other purposes or is turned off. Turning off is provided either by a line formed of a second metal layer that is connected between the antenna and ground, or by a reversed biased diode (118) and a parallel capacitor (120) that are connected between the gate of the protection transistor and ground. The present invention includes the method of manufacturing the protection device.

    TWO BIT NON-VOLATILE ELECTRICALLY ERASABLE AND PROGRAMMABLE SEMICONDUCTOR MEMORY CELL UTILIZING ASYMMETRICAL CHARGE TRAPPING
    43.
    发明公开
    TWO BIT NON-VOLATILE ELECTRICALLY ERASABLE AND PROGRAMMABLE SEMICONDUCTOR MEMORY CELL UTILIZING ASYMMETRICAL CHARGE TRAPPING 审中-公开
    两位不挥发可编程电子擦除和半导体存储单元具有不对称LADUNGSABFANG

    公开(公告)号：EP1010182A2

    公开(公告)日：2000-06-21

    申请号：EP98936654.7

    申请日：1998-08-02

    申请人： Saifun Semiconductors Ltd

    发明人： EITAN, Boaz

    IPC分类号： G11C14/00

    CPC分类号： H01L29/7887 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/28282 ,  H01L29/7885 ,  H01L29/7923

    摘要： A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bitS of information having a nonconducting charge trapping dielectric, such as silicon nitride (20), sandwiched between two silicon dioxide layers (18, 22) acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device. The noncoducting dielectric layer functions as an electrical charge trapping medium. A conducting gate electrode (24) is placed over the upper silicon dioxide layer (22). A left and right bit are stored in physically different areas of the charge trapping layer, near left and right regions of the memory cell, respectively. Each bit of the memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and to either the left or the right region while the other region is grounded.

    METHOD, SYSTEM AND CIRCUIT FOR PROGRAMMING A NON-VOLATILE MEMORY ARRAY
    46.
    发明公开
    METHOD, SYSTEM AND CIRCUIT FOR PROGRAMMING A NON-VOLATILE MEMORY ARRAY 审中-公开
    方法，系统及电路编程的非易失性存储器阵列

    公开(公告)号：EP1683159A4

    公开(公告)日：2007-03-21

    申请号：EP04791843

    申请日：2004-10-27

    申请人： SAIFUN SEMICONDUCTORS LTD

    发明人： COHEN GUY ,  EITAN BOAZ

    IPC分类号： G11C16/34 ,  G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10

    CPC分类号： G11C11/5628 ,  G11C11/5671 ,  G11C16/10 ,  G11C16/3468

    摘要： The present invention is a multi-phase method, circuit and system for programming non-volatile memory ('NVM') cells in an NVM array (100). The present invention may include a controller (110) to determine when, during a first programming phase (2000), one or more NVM cells of a first set of cells reaches or exceeds a first intermediate voltage, and to cause a charge pump circuit (130) to apply to a terminal of the one or more cells (100) in the first set second phase programming (3000) pulses to induce relatively greater threshold voltage changes in cells having less stored charge than in cells having relatively more stored charge.

    A METHOD CIRCUIT AND SYSTEM FOR DETERMINING A REFERENCE VOLTAGE
    48.
    发明公开
    A METHOD CIRCUIT AND SYSTEM FOR DETERMINING A REFERENCE VOLTAGE 审中-公开
    VERFAHREN，SCHALTUNG UND SYSTEM ZUM BESTIMMEN EINER REFERENZSPANNUNG

    公开(公告)号：EP1685571A4

    公开(公告)日：2006-12-20

    申请号：EP04791844

    申请日：2004-10-27

    申请人： SAIFUN SEMICONDUCTORS LTD

    发明人： COHEN GUY

    IPC分类号： G11C29/00 ,  G06F11/10 ,  G06K20060101 ,  G11C7/00 ,  G11C7/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/28 ,  G11C16/30 ,  G11C16/34 ,  G11C17/00 ,  G11C29/24 ,  G11C29/50

    CPC分类号： G11C11/5642 ,  G06F11/1008 ,  G11C16/28 ,  G11C16/30 ,  G11C16/3436 ,  G11C29/24 ,  G11C29/50 ,  G11C2029/0409 ,  G11C2029/5004 ,  G11C2211/5634

    摘要： The present invention is a method, circuit and system for determining a reference voltage. Some embodiments of the present invention relate to a system, method and circuit for establishing a set of operating reference cells to be used in operating (e.g. reading) cells in an NVM block or array. As part of the present invention, at least a subset of cells of the NVM block or array may be read using each of two or more sets of test reference cells, where each set of test reference cells may generate or otherwise provide reference voltages at least slightly offset from each other set of test reference cells. For each set of test reference cells used to read the at least a subset of the NVM block, a read error rate may be calculated or otherwise determined. A set of test reference cells associated with a relatively low read error rate may be selected as the set of operating reference cells to be used in operating (e.g. reading) other cells, outside the subset of cells, in the NVM block or array. In a further embodiment, the selected set of test reference cells may be used to establish an operating set of reference cells having reference voltages substantially equal to those of the selected test set.

    摘要翻译： 本发明是用于确定参考电压的方法，电路和系统。 本发明的一些实施例涉及用于建立在NVM块或阵列中操作（例如读取）单元中使用的一组操作参考单元的系统，方法和电路。 作为本发明的一部分，可以使用两组或更多组测试参考单元中的每一个读取NVM块或阵列的至少一个单元子集，其中每组测试参考单元可以生成或以其他方式提供参考电压 从每组其他测试参考单元略微偏移。 对于用于读取NVM块的至少一个子集的每组测试参考单元，可以计算或以其他方式确定读取错误率。 可以选择与相对低的读取错误率相关联的一组测试参考单元作为在NVM块或阵列中操作（例如读取）位于单元子集外部的其他单元的一组操作参考单元。 在进一步的实施例中，选定的一组测试参考单元可以用于建立具有基本上等于所选测试集的参考电压的参考电压的操作集合。

    Threshold voltage shift in NROM cells
    49.
    发明公开
    Threshold voltage shift in NROM cells 审中-公开
    Schwellenspannungsveränderungbei NROM-Zellen

    公开(公告)号：EP1713129A2

    公开(公告)日：2006-10-18

    申请号：EP06112462.4

    申请日：2006-04-11

    申请人： Saifun Semiconductors Ltd.

    发明人： Lusky, Eli

    IPC分类号： H01L29/792

    CPC分类号： G11C16/0475 ,  G11C11/5671 ,  G11C16/349 ,  H01L29/7923

    摘要： An NROM (nitride read only memory) cell, which is programmed by channel hot electron injection and erased by hot hole injection, includes a charge trapping structure formed of: a bottom oxide layer, a charge trapping layer; and a top oxide layer. The bottom oxide layer is no thicker than that which provides margin stability.

    摘要翻译： 通过通道热电子注入并通过热空穴注入而擦除的NROM（氮化物只读存储器）单元（128）包括电荷俘获结构，其由下部氧化物层（130），电荷俘获层（110） ）; 和顶部氧化物层（111）。 底部氧化物层（130）不比提供边界稳定性更厚。