公开(公告)号：EP0206695A2

公开(公告)日：1986-12-30

申请号：EP86304574

申请日：1986-06-13

Applicant: FUJITSU LTD

Inventor： TAKEGUCHI TETSUJI

IPC: G11C17/00 ,  G11C8/12 ,  G11C16/08 ,  G11C29/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/34 ,  G11C29/50

CPC classification number: G11C29/025 ,  G11C8/12 ,  G11C16/04 ,  G11C16/08 ,  G11C29/02 ,  G11C29/34 ,  G11C29/50 ,  G11C2029/5004 ,  G11C2029/5006

Abstract: In order to facilitate a test of the operations of a semiconductor memory device, the semiconductor memory device includes a line selection checking unit (ALL-SELECTED STATE CHECK CIRCUIT) coupled to a cell array and column gates to form a logic gate circuit unit consisting of a plurality of transistors, the gates of the transistors being connected to word lines (XO, X1, X2) or bit lines (YO, Y1, Y2). The line selection checking unit has a voltage or current detection portion (NODE OUTPUT) connected to a pad (PM, P1) for detecting an output voltage or current of the line selection checking unit.

公开(公告)号：EP0162418A2

公开(公告)日：1985-11-27

申请号：EP85106019.4

申请日：1985-05-15

Applicant: ADVANTEST CORPORATION

Inventor： Shimizu, Masao

IPC: G11C29/00

CPC classification number: G11C29/021 ,  G01R31/3004 ,  G01R31/31919 ,  G01R31/3193 ,  G11C29/02 ,  G11C29/50 ,  G11C29/56 ,  G11C2029/5006

Abstract: The equipment of the present invention is a semiconductor tester in which an address is generated by a test pattern generator (101) in synchronism with an operating clock from a timing generator (102), the address is applied to a memory (112) under test and a check is made to determine if the power source current to the memory undertest is larger than a predetermined value. A current value deciding circuit (220) is provided, by which the power source current value is detected, and it is decided by a comparator whether the detected current value is greater than the predetermined value or not. The decision result is output at the timing of an output timing signal from the timing generator.

Abstract translation: 本发明的设备是一种半导体测试器，其中地址由测试码型发生器（101）与来自定时发生器（102）的操作时钟同步产生，该地址被施加到测试中的存储器（112） 并进行检查以确定到存储器基板的电源电流是否大于预定值。 提供电流值确定电路（220），通过该电路值检测电源电流值，并由比较器确定检测到的电流值是否大于预定值。 在来自定时发生器的输出定时信号的定时处输出判定结果。

公开(公告)号：EP1436815B1

公开(公告)日：2010-03-03

申请号：EP02759714.5

申请日：2002-09-17

Applicant: Kilopass Technology, Inc.

Inventor： PENG, Jack Zezhong

IPC: G11C17/16 ,  H01L23/525

CPC classification number: H01L27/11206 ,  G11C11/5692 ,  G11C17/16 ,  G11C29/50 ,  G11C2029/5006 ,  H01L27/112 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1774531A4

公开(公告)日：2008-09-03

申请号：EP05778107

申请日：2005-08-02

Applicant: ANALOG DEVICES INC

Inventor： BRENNAN OLIVER ,  DOYLE DENIS

IPC: G11C17/00 ,  G11C17/18

CPC classification number: G11C29/027 ,  G11C17/14 ,  G11C17/16 ,  G11C17/18 ,  G11C29/50 ,  G11C2029/5006

Abstract: A programmable read only memory includes a matrix of semi-fusible link memory cells, each including a semi-fusible link having an intact impedance and a blown impedance; a bit line voltage supply switching circuit for applying a current to at least one selected bit line; a word line address decoder for selecting a word line; and a program control logic circuit for blowing the semi-fusible links in the memory cells identified by the intersection of the selected word and bit lines; a method is disclosed of testing programmed and unprogrammed read only memory.

公开(公告)号：EP1436815A4

公开(公告)日：2007-04-11

申请号：EP02759714

申请日：2002-09-17

Applicant: KILOPASS TECHNOLOGIES INC

Inventor： PENG JACK ZEZHONG

IPC: G11C17/08 ,  G11C17/16 ,  G11C11/56 ,  G11C29/50 ,  H01L21/8246 ,  H01L23/525 ,  H01L27/10 ,  H01L27/112

CPC classification number: H01L27/11206 ,  G11C11/5692 ,  G11C17/16 ,  G11C29/50 ,  G11C2029/5006 ,  H01L27/112 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory cell (300) having a data storage element (115) constructed around an ultra-thin dielectric (312) is used to store information by stressing the ultra-thin dielectric (312) into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell (300). The memory cell (300) is read by sensing the current drawn by the cell (300). A suitable ultra-thin dielectric (312) is high quality gate oxide of about 50 Å thickness or less.

公开(公告)号：EP1620859A4

公开(公告)日：2007-02-21

申请号：EP04751987

申请日：2004-05-12

Applicant: ECOLE POLYTECH

Inventor： PORTMANN LIONEL ,  KAYAL MAHER ,  PASTRE MARC ,  BLAGOJEVIC MARIJA ,  DECLERCQ MICHEL

IPC: G11C7/14 ,  G11C11/403 ,  G11C11/404 ,  G11C11/4099 ,  G11C16/28 ,  G11C29/02

CPC classification number: G11C29/028 ,  G11C7/14 ,  G11C11/401 ,  G11C11/4099 ,  G11C16/28 ,  G11C29/02 ,  G11C29/12005 ,  G11C2029/5006 ,  G11C2211/4016

Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is a technique and circuitry for reading data that is stored in memory cells. In one embodiment of this aspect, the present invention is a technique and circuitry for generating a reference current that is used, in conjunction with a sense amplifier, to read data that is stored in memory cells of a DRAM device. The technique and circuitry for generating a reference current may be implemented using an analog configuration, a digital configuration, and/or combinations of analog and digital configurations.

公开(公告)号：EP0997913B1

公开(公告)日：2005-08-10

申请号：EP98830654.4

申请日：1998-10-29

Applicant: STMicroelectronics S.r.l.

Inventor： Riva, Marco ,  Rolandi, Paolo ,  Montanaro, Massimo

IPC: G11C29/00 ,  G11C11/56 ,  G06F11/20

CPC classification number: G11C29/50 ,  G06F2201/81 ,  G11C11/56 ,  G11C11/5642 ,  G11C2029/5006 ,  G11C2211/5634

Abstract: A method for testing virgin memory cells in a multilevel memory device which comprises a plurality of memory cells, the particularity of which consists of the fact that it comprises the steps of: reading the individual memory cells that constitute a memory device and comparing each one of these memory cells with at least one reference memory cell at a time, so as to determine whether the threshold of the memory cells is lower than the threshold of the at least one reference memory cell or not; determining the number of the memory cells whose threshold is higher than the threshold of the at least one reference cell; the at least one reference memory cell being chosen with a gradually higher threshold; when the number of memory cells whose threshold is higher than a given reference threshold is found to be sufficiently lower than the number of redundancy memory cells provided in the memory device, assuming the given reference threshold as lower reference threshold for the memory device, determining a statistical distribution of the thresholds of the memory cells.

公开(公告)号：EP1560223A2

公开(公告)日：2005-08-03

申请号：EP04017679.4

申请日：2004-07-26

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Perner, Frederick A. ,  Bhattacharyya, Manoj K.

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1675 ,  G11C29/021 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50008 ,  G11C2029/5002 ,  G11C2029/5006

Abstract: A magnetic memory cell write current threshold detector [510]. The magnetic memory cell write current threshold detector [510] includes a first MRAM test cell [512] receiving a write current and sensing when the write current exceeds a first threshold, and a second MRAM test cell [514] receiving the write current and sensing when the write current exceeds a second threshold.

Abstract translation: 磁存储器单元写入电流阈值检测器[510]。 磁存储器单元写入电流阈值检测器[510]包括接收写入电流并感测何时写入电流超过第一阈值的第一MRAM测试单元[512]，以及接收写入电流和感测的第二MRAM测试单元[514] 当写入电流超过第二阈值时。

公开(公告)号：EP1403874B1

公开(公告)日：2005-07-27

申请号：EP03255479.2

申请日：2003-09-02

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Tran, Lung T. ,  Bhattacharyya, Manoj K.

IPC: G11C11/16

CPC classification number: G11C29/028 ,  G11C11/15 ,  G11C11/16 ,  G11C29/50 ,  G11C2029/5002 ,  G11C2029/5006

公开(公告)号：EP1333446A3

公开(公告)日：2004-08-18

申请号：EP03250538.0

申请日：2003-01-29

Applicant: STMicroelectronics, Inc.

Inventor： McClure, David C.

IPC: G11C29/00

CPC classification number: G11C29/50 ,  G11C11/22 ,  G11C2029/5006

Abstract: A test circuit and method are disclosed for testing memory cells of a ferroelectric memory device having an array of ferroelectric memory cells. The test circuitry is coupled to the bit lines, for selectively determining the voltage levels appearing on the bit lines based on a measured current level and providing externally to the ferroelectric memory device an electrical signal representative of the sensed voltage levels. In this way, ferroelectric memory cells exhibiting degraded performance may be identified.