Glass-sealed multichip process
    51.
    发明公开
    Glass-sealed multichip process 失效
    在玻璃封装多个芯片的方法。

    公开(公告)号:EP0013815A1

    公开(公告)日:1980-08-06

    申请号:EP79302905.9

    申请日:1979-12-14

    IPC分类号: H01L21/56 H01L23/28

    摘要: The preferred embodiment of the invention comprises a glass sealed thyristor (10) and a method for simultaneously constructing a plurality of thyristors on a common semiconductor wafer (46). The thyristor utilizes a body of semiconductor material with the cathode and base regions (20, 24) extending to one major surface (14) and the anode region (22) extending to the second major surface (16). A groove (36) is etched in the first surface of the body of semiconductor material to expose the PN junction formed at the interface of the cathode emitter and cathode emitter base regions. A second groove (40) is etched in the second major surface to expose the PN junction formed at the interface of the anode emitter region and the anode emitter base region. Ring shaped glass members (42). are fused to the body of semiconductor material to form seals providing environmental protection for the PN junctions exposed by etching the grooves in the major surfaces of the body of semiconductor material. A plurality of thyristors can be simultaneously constructed on a common semiconductor wafer.

    Process of making a MESA bipolar transistor with self-aligned base and emitter regions
    52.
    发明公开
    Process of making a MESA bipolar transistor with self-aligned base and emitter regions 失效
    具有自对准基和发射区的MESA双极晶体管的制造方法

    公开(公告)号:EP0004292A3

    公开(公告)日:1979-11-14

    申请号:EP79100546

    申请日:1979-02-23

    IPC分类号: H01L21/00 H01L29/10 H01L29/72

    摘要: Ce transistor est réalisé à partir d'une structure classique comportant un substrat (21), une région de sous-collecteur (22) associée à une région de traversée de collecteur (24), une couche épitaxiale (20) servant de région de collecteur et une couche de base (26) et des murs d'isolement (23). Dans un mode préféré on forme une couche d'émetteur (27) sur la couche de base. Puis une couche de masquage (28) est formée sur la couche d'émetteur, elle definit une ouverture autour de la région destinée à constituer l'émetteur. Les parties exposées de la structure sont attaquées ce qui définit avec précision la région d'émetteur (27), et la région de base (26). On forme alors par implantation ionique la région de contact de base (32). Les régions d'émetteur, de base et de contact de base sont donc auto-alignées. La structure est passivée par les régions d'oxyde encastré (33). On forme enfin les contacts ohmiques nécessaires. Ce procédé permet l'obtention de transistors très rapides et à grande densité d'intégration utiles dans les applications aux calculateurs.

    摘要翻译: 该晶体管由常规结构形成,该结构包括基板(21),与集电极通路区域(24)相关联的子集电极区域(22),用作集电极区域的外延层(20)和基极层(26) 墙壁(23)。 在优选实施例中,在基底层上形成发射极层(27)。 然后在发射极层上形成掩模层(28); 它限定了旨在构成发射器的区域周围。 结构的暴露部分受到攻击; 这准确地限定了发射极区域(27)和基极区域(26)。 然后使用离子注入形成基底接触区域(32)。 因此,发射极,基极和基极接触区域是自对准的。 该结构被嵌入的氧化物区域钝化(33)。 最后,形成所需的电阻触点。 该方法允许生产具有高集成密度的非常快速的晶体管,其在计算机的应用中是有用的。

    A BIPOLAR JUNCTION TRANSISTOR STRUCTURE
    54.
    发明公开
    A BIPOLAR JUNCTION TRANSISTOR STRUCTURE 审中-公开
    具有双极连接晶体管结构

    公开(公告)号:EP2954557A1

    公开(公告)日:2015-12-16

    申请号:EP14705557.8

    申请日:2014-02-07

    申请人: Wood, John

    发明人: Wood, John

    摘要: A bi-directional bipolar junction transistor (BJT) comprising a base region with a first conductivity type, first and second collector/emitter (CE) regions, each of a second conductivity type adjacent to opposite ends of the base region, wherein the base is lightly doped relative to the collector/emitter regions. There can also be a second transistor whose input/output is connected to a base connection of the first transistor. The base region can be wider in a direction between said ends of said base region than each of said CE regions. The transistor can also have a buried layer of the second conductivity type disposed between the CE region and the base region. The transistor may have a field stop layer of the first conductivity type formed between the emitter region and the base region. The bipolar junction transistor can be used in a driver circuit, a matrix converter or a relay circuit. Also provided is a circuit breaker which may comprise a bipolar junction transistor.

    BIPOLAR JUNCTION TRANSISTOR WITH SPACER LAYER AND METHOD OF MANUFACTURING THE SAME
    55.
    发明公开
    BIPOLAR JUNCTION TRANSISTOR WITH SPACER LAYER AND METHOD OF MANUFACTURING THE SAME 有权
    BIPOLARTRANSISTOR MIT ABSTANDHALTERSCHICHT UND HERSTELLUNGSVERFAHRENDAFÜR

    公开(公告)号:EP2761660A1

    公开(公告)日:2014-08-06

    申请号:EP12700407.5

    申请日:2012-01-18

    摘要: New designs for silicon carbide (SiC) bipolar junction transistors (BJTs) and new methods of manufacturing such SiC BJTs are provided. The SiC BJT comprises a collector region (220), a base region (240) and an emitter region (260) arranged as a stack, the emitter region and part of the base region forming a mesa. The intrinsic part of the base region includes a first portion having a first doping concentration and a second portion having a second doping concentration lower than the first doping concentration. Further, the second portion is vertically arranged between the first portion and the emitter region in the stack.

    摘要翻译: 描述了碳化硅(SiC)双极结晶体管(BJT)的新设计和制造这种SiC BJT的新方法。 SiC BJT包括集电极区域,基极区域和作为堆叠设置的发射极区域,发射极区域和基极区域的一部分形成台面。 基区的本征部分包括具有第一掺杂浓度的第一部分和具有低于第一掺杂浓度的第二掺杂浓度的第二部分。 此外,第二部分垂直地设置在堆叠中的第一部分和发射极区域之间。

    SEMICONDUCTOR SWITCH DEVICES AND THEIR MANUFACTURE
    59.
    发明授权
    SEMICONDUCTOR SWITCH DEVICES AND THEIR MANUFACTURE 有权
    半导体电路及其制备方法

    公开(公告)号:EP0979530B1

    公开(公告)日:2009-04-22

    申请号:EP99901813.8

    申请日:1999-02-04

    申请人: NXP B.V.

    摘要: In a semiconductor switch device such as an NPN transistor (T) or a power switching diode (D), a multiple-zone first region (1) of one conductivity type forms a switchable p-n junction (12) with a second region (2) of opposite conductivity type. In accordance with the invention, this first region (1) includes three distinct zones, namely a low-doped zone (23), a high-doped zone (25), and an intermediate additional zone (24). The low-doped zone (23) is provided by a semiconductor body portion (11) having a substantially uniform p-type doping concentration (P-) and forms the p-n junction (12) with the second region (2). The distinct additional zone (24) is present between the low-doped zone (23) and the high-doped zone (25). This triple-zone formation for the first region (1) permits an improvement in switching behaviour, e.g. in terms of fall-time and energy dissipation during turn-off of the device (T, D). A very low doping (P-) can be used for low-doped zone (23) so that, in the off-state of the device (T, D), this zone (23) and also the additional zone (24) can be fully depleted. The additional zone (24) having its additional doping concentration provides a path for extracting residual charge carriers from the low-doped zone (23) when the device (T, D) is being switched off.