公开(公告)号：EP2138452A1

公开(公告)日：2009-12-30

申请号：EP09290472.1

申请日：2009-06-22

Applicant: Commissariat à l'Energie Atomique

Inventor： Perruchot, François ,  Diem, Bernard ,  Larrey, Vincent ,  Clavelier, Laurent ,  Defay, Emmanuel

IPC: B81C1/00

CPC classification number: B81C1/00238 ,  B81B2201/0271 ,  B81C1/00357 ,  B81C2201/0115 ,  B81C2201/014 ,  B81C2201/0191

Abstract: L'invention est relative à un procédé de fabrication d'un dispositif électromécanique comprenant un élément actif, caractérisé en ce qu'il comporte :
a) la réalisation d'une première couche d'arrêt monocristalline (2) sur une couche monocristalline (1') d'un premier substrat (1),
b) l'épitaxie sur ladite première couche d'arrêt (2), d'une couche mécanique monocristalline (3) en au moins un matériau différent de celui de la couche d'arrêt (2),
c) la réalisation sur ladite couche active (3), d'une couche sacrificielle (4),
d) la réalisation d'une couche d'adhésion (50) sur la couche sacrificielle (4),
e) le collage d'un deuxième substrat (6) sur la couche d'adhésion (50)
f) l'élimination du premier substrat (1) et de la couche d'arrêt (2) pour mettre à nu la surface (3 1 ) de la couche mécanique (3) opposée à la couche sacrificielle (4), l'élément actif étant réalisé par au moins une partie de la couche mécanique (3).

Abstract translation: 该方法涉及epitaxying单晶阻挡层，其中所述阻挡层由硅锗或多孔硅或掺杂硅上的单晶硅机械层（3）。 牺牲层（4）被实现的层（3）和粘附层（50）被实现的层（4），其中在基板（6）被粘合层（50）上的。 将单晶硅基板和阻挡层被消除以暴露层（3）相对的层（4）的表面（3-1），并且在activeElement由层（3）的一部分实现。

公开(公告)号：EP1880977A3

公开(公告)日：2009-10-28

申请号：EP07112635.3

申请日：2007-07-17

Applicant: Honeywell International Inc.

Inventor： Klein, Jonathan L. ,  Pilchowski, Jorg

IPC: B81C1/00

CPC classification number: B81C1/00579 ,  B81C2201/0107 ,  B81C2201/014

Abstract: Micro-electromechanical systems (MEMS) pre-fabrication products and methods for forming MEMS devices using silicon-on-metal (SOM) wafers. An embodiment of a method may include the steps of bonding a patterned SOM wafer to a cover wafer (46), thinning the handle layer of the SOM wafer (48), selectively removing the exposed metal layer (50), and either continuing with final metallization (64) or cover bonding to the back of the active layer (62).

公开(公告)号：EP1943184A1

公开(公告)日：2008-07-16

申请号：EP06808404.5

申请日：2006-11-02

Applicant: CAVENDISH KINETICS LIMITED

Inventor： VAN KAMPEN, Robert ,  KAZINCZI, Robert

IPC: B81B3/00 ,  G11C23/00 ,  G11C11/50 ,  H01H1/00

CPC classification number: H01H59/0009 ,  B81C1/0015 ,  B81C2201/014 ,  B81C2201/0176 ,  G11C23/00 ,  H01H51/12

Abstract: A non-volatile memory device and method of manufacturing a non-volatile micro-electromechanical memory cell. The method comprises the first step of depositing a first layer of sacrificial material on a substrate by use of Atomic Layer Deposition The second step of the method is providing a cantilever (101) over at least a portion of the first layer of sacrificial material. The third step is depositing, by use of Atomic Layer Deposition, a second layer of sacrificial material over the first layer of sacrificial material and over a portion of the cantilever such that a portion of the cantilever is surrounded by sacrificial material. The fourth step is providing a further layer material (107) which covers at least a portion of the second layer of sacrificial material. Finally, the last step is etching away the sacrificial material surrounding the cantilever, thereby defining a cavity (102) in which the cantilever is suspended.

公开(公告)号：EP1907316A1

公开(公告)日：2008-04-09

申请号：EP06788039.3

申请日：2006-07-19

Applicant: Qualcomm Mems Technologies, Inc.

Inventor： SASAGAWA, Teruo ,  CHUI, Clarence ,  KOTHARI, Manish ,  GANTI, Surya, Prakash ,  SAMPSELL, Jeffrey, B.

IPC: B81B3/00

CPC classification number: G02B26/0841 ,  B81B2201/042 ,  B81B2203/0307 ,  B81C1/00595 ,  B81C2201/014 ,  G02B26/001

Abstract: A microelectromechanical systems device having support structures formed of sacrificial material surrounded by a protective material. The microelectromechanical systems device includes a substrate having an electrode formed thereon. Another electrode is separated from the first electrode by a cavity and forms a movable layer, which is supported by support structures formed of a sacrificial material.

公开(公告)号：EP1754683A1

公开(公告)日：2007-02-21

申请号：EP05017927.4

申请日：2005-08-18

Applicant: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.

Inventor： Schenk, Harald, Dr.-Ing.

IPC: B81B3/00 ,  G02B26/08 ,  B01L3/00

CPC classification number: G02B26/0825 ,  B01L3/5027 ,  B81B2201/036 ,  B81B2203/0127 ,  B81B2203/0361 ,  B81B2207/07 ,  B81C1/00182 ,  B81C2201/014 ,  F04B43/043 ,  G02B26/0841

Abstract: Die Erfindung betrifft Mikro-Elektromechanische Elemente, die vielfältig mit geringfügigen Modifikationen in der Mikromechanik, -optik und auch -fluidik eingesetzt werden können. Sie sollen kostengünstig hergestellt werden können und für verschiedene Applikationen anpassbar sein. Die erfindungsgemäßen Elemente sind dabei so ausgebildet, dass auf einem Substrat eine elastisch verformbare Membran aus einem zumindest bereichsweise elektrisch leitenden Werkstoff so befestigt ist, dass zwischen Substrat und Membran ein Hohlraum oder ein Spaltbereich mittels Abstandshaltern ausgebildet ist. Ein oder mehrere Abstandshalter sind aus einem dielektrischen polymeren Werkstoff gebildet. Am Substrat ist mindestens ein Kontaktelement vorhanden, das an eine elektrische Spannungsquelle angeschlossen ist.

Abstract translation: 微机电元件在基板上具有由导电材料制成的柔性延性膜片。 在基板（1）和隔膜（2）之间，由介电聚合材料的多个间隔物（4）提供空腔（3）或间隙。 在基板上设有一个连接到电源上的接触元件。 触点可以单独控制。 触点和/或部分用于局部限定的布置在基板上的隔膜的柔性变形。

公开(公告)号：EP1640768A1

公开(公告)日：2006-03-29

申请号：EP05255661.0

申请日：2005-09-14

Applicant: IDC, LLC

Inventor： Chui, Clarence ,  Gally, Brian J. ,  Kothari, Manish ,  Tung, Ming-Hau

IPC: G02B26/00 ,  B81B3/00

CPC classification number: G02B26/001 ,  B81B2201/042 ,  B81C1/00793 ,  B81C1/00801 ,  B81C2201/014

Abstract: The fabrication of a MEMS device such as an interferometric modulator is improved by employing an etch stop layer (44) between a sacrificial layer (46) and a mirror layer (38). The etch stop may reduce undesirable over-etching of the sacrificial layer and the mirror layer. The etch stop layer may also serve as a barrier layer, buffer layer, and/or template layer.

Abstract translation: 通过在牺牲层（46）和镜层（38）之间采用蚀刻停止层（44）来改善诸如干涉式调制器之类的MEMS器件的制造。 蚀刻停止可减少对牺牲层和镜层的不希望的过蚀刻。 蚀刻停止层也可以用作阻挡层，缓冲层和/或模板层。

公开(公告)号：EP1428255A1

公开(公告)日：2004-06-16

申请号：EP02798102.6

申请日：2002-08-29

Applicant: Silicon Light Machines

Inventor： BRUNER, Mike

IPC: H01L23/02 ,  H01L21/302 ,  H01L21/461

CPC classification number: B81C1/00484 ,  B81B2201/0271 ,  B81B2203/0136 ,  B81C1/00246 ,  B81C1/00333 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2203/0136 ,  B81C2203/0735

Abstract: The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. The multi-layer structure has a capping layer (211) that preferably comprises silicon oxide and/or silicon nitride and which is formed over an etch resistant substrate (203). A patterned device layer (206), preferably comprising silicon nitride, is embedded in a sacrificial material (205, 209), preferably comprising polysilicon, and is disposed between the etch resistant substrate (203) and the capping layer (211). Access trenches or holes (219) are formed into the capping layer (211) and the sacrificial material (205, 209) is selectively etched through the access trenches (219) such that portions of the device layer (206) are released from the sacrificial material (205, 209). The etchant preferably comprises a noble gas fluoride NgF2x (wherein Ng = Xe, Kr or Ar: and where x = 1, 2 or 3). After etching that sacrificial material (205, 209), the access trenches (219) are sealed to encapsulate (241) released portions the device layer (206) between the etch resistant substrate (203) and the capping layer (211). The current invention is particularly useful for fabricating MEMs devices, multiple cavity devices and devices with multiple release features.

公开(公告)号：EP1364398A1

公开(公告)日：2003-11-26

申请号：EP02708936.6

申请日：2002-01-02

Applicant: The Charles Stark Draper Laboratory, INC.

Inventor： BORENSTEIN, Jeffrey

IPC: H01L21/46 ,  C23F1/00

CPC classification number: B81C1/00119 ,  B81B2201/0235 ,  B81C1/00357 ,  B81C2201/0132 ,  B81C2201/014 ,  B81C2201/019 ,  B81C2201/0191

Abstract: The invention provides a general fabrication method for producing MicroElectroMechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI). One first obtains an SOI wafer that has (i) a handle layer, (ii) a dielectric layer, and (iii) a device layer. A mesa etch has been made on the device layer of the SOI wafer and a structural etch has been made on the dielectric layer of the SOI wafer. One then obtains a substrate (such as glass or silicon), where a pattern has been etched onto the substrate. The SOI wafer and the substrate are bonded together. Then the handle layer of the SOI wafer is removed, followed by the dielectric layer of the SOI wafer.

公开(公告)号：EP0955668A3

公开(公告)日：2003-05-07

申请号：EP99109110.9

申请日：1999-05-07

Applicant: Rockwell Science Center, LLC

Inventor： Yao, Jun J. ,  Anderson, Robert J.

IPC: H01L21/00 ,  B81B3/00 ,  B81C1/00

CPC classification number: B81C1/00484 ,  B81B2203/0118 ,  B81C2201/0108 ,  B81C2201/014 ,  B81C2201/019

Abstract: The present invention relates to a fabrication process for manufacture of micro electromechanical (MEM) devices such as cantilever support beams. This fabrication process requires only two lithographic masking steps and offers moveable electromechanical devices with high electrical isolation. A preferred embodiment of the process uses electrically insulating glass substrate (102) as the carrier substrate and single crystal silicon (108) as the MEM component material. The process further includes deposition of an optional layer of insulating material (110) such as silicon dioxide on top of a layer of doped silicon (108) grown on a silicon substrate. The silicon dioxide (110) is epoxy bonded to the glass substrate (102) to create a silicon-silicon dioxide-epoxy-glass structure (200). The silicon is patterned using anisotropic plasma dry etching techniques. A second patterning then follows to pattern the silicon dioxide layer (110) and an oxygen plasma etch is performed to undercut the epoxy film (120) and to release the silicon MEM component. This two-mask process provides single crystal silicon MEMs with electrically isolated MEM component. Retaining silicon dioxide insulating material (110) in selected areas mechanically supports the MEM component.

公开(公告)号：EP1233927A4

公开(公告)日：2003-01-08

申请号：EP00980528

申请日：2000-11-17

Applicant: UNIV CALIFORNIA

Inventor： HANSFORD DEREK ,  FERRARI MAURO

IPC: B82B3/00 ,  B01D67/00 ,  B01D69/02 ,  B01D71/02 ,  B81B3/00 ,  B81C1/00 ,  B01D63/00 ,  B01J29/06 ,  B82B1/00 ,  C01B37/00

CPC classification number: B81C1/00158 ,  B01D67/0058 ,  B01D67/0062 ,  B01D67/0072 ,  B01D69/02 ,  B01D71/02 ,  B01D71/022 ,  B01D2325/02 ,  B01D2325/04 ,  B01D2325/08 ,  B81B2201/06 ,  B81B2201/10 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2201/053

Abstract: A method of forming a membrane with nanometer scale pores includes forming a sacrificial etch stop layer on a substrate. A base layer is constructed on the sacrificial etch stop layer. Micrometer scale pores are formed within the base layer. A sacrificial base layer is built on the base layer. The sacrificial base layer is removed from selected regions of the base layer to define nanometer scale pores within the base layer. The resultant membrane has sub-fifty nanometer pores formed within it.