公开(公告)号：EP3174825A1

公开(公告)日：2017-06-07

申请号：EP15739302.6

申请日：2015-07-24

Applicant: ams International AG

Inventor： BESLING, Willem Frederik Adrianus ,  PIJNENBURG, Remco Henricus Wilhelmus ,  VAN DER AVOORT, Casper ,  OLDSEN, Marten ,  GOOSSENS, Martijn

IPC: B81C1/00 ,  G01L9/00

CPC classification number: B81C1/00158 ,  B81C1/00246 ,  B81C2201/014 ,  G01L9/0042 ,  G01L9/0072 ,  G01L9/0073 ,  G01L9/12 ,  H01L29/84

Abstract: Embodiments of a method for forming a suspended membrane include depositing a first electrically conductive material above a sacrificial layer and within a boundary trench. The first electrically conductive material forms a corner transition portion above the boundary trench. The method further includes removing a portion of the first electrically conductive material that removes at least a portion of uneven topography of the first electrically conductive material. The method further includes depositing a second electrically conductive material. The second electrically conductive material extends beyond the boundary trench. The method further includes removing the sacrificial layer through etch openings and forming a cavity below the second electrically conductive material. The first electrically conductive material defines a portion of a sidewall boundary of the cavity.

Abstract translation: 用于形成悬浮膜的方法的实施例包括在牺牲层上方和边界沟槽内沉积第一导电材料。 第一导电材料在边界沟槽上方形成拐角过渡部分。 该方法还包括去除去除第一导电材料的不平坦形貌的至少一部分的第一导电材料的一部分。 该方法还包括沉积第二导电材料。 第二导电材料延伸超过边界沟槽。 该方法还包括通过蚀刻开口去除牺牲层并在第二导电材料下方形成空腔。 第一导电材料限定了空腔的侧壁边界的一部分。

公开(公告)号：EP2138454A1

公开(公告)日：2009-12-30

申请号：EP09290474.7

申请日：2009-06-22

Applicant: Commissariat à l'Energie Atomique

Inventor： Perruchot, François ,  Diem, Bernard ,  Larrey, Vincent ,  Clavelier, Laurent ,  Defay, Emmanuel

IPC: B81C1/00 ,  H03H3/007

CPC classification number: B81C1/00595 ,  B81B2201/0271 ,  B81C2201/0109 ,  B81C2201/014

Abstract: L'Invention se rapporte à un procédé de réalisation d'un composant à partir d'un substrat hétérogène comportant une première et une deuxième parties en au moins un matériau monocristallin, et une couche sacrificielle constituée par au moins un empilement d'au moins une couche de Si monocristallin située entre deux couches de SiGe monocristallin, cet empilement étant disposé entre lesdites première et deuxième partie en matériau monocristallin, caractérisé en ce qu'il consiste à graver ledit empilement en réalisant :
e) au moins une ouverture (20) dans la première et/ou la deuxième parties et la première et/ou la deuxième couche de SiGe de façon à déboucher sur la couche de Si,
f) une élimination de toute ou partie de la couche de Si.

Abstract translation: 基板具有由位于单晶硅 - 锗层之间的单晶硅层（3）的叠层构成的牺牲层。 堆栈是位于两个单晶部分之间。 一个单晶的部分之一是含有一个硅 - 锗材料的外延相容。 另一单晶硅部分是硅，钛酸锶/锆钛酸铅，或锶/钌酸锶/锆钛酸铅中选择。 因此独立权利要求中包括了以下内容：为了实现异质衬底（2）的方法，用于从异质衬底实现一个部件（1）的方法。

公开(公告)号：EP2121515A2

公开(公告)日：2009-11-25

申请号：EP08734374.5

申请日：2008-03-13

Applicant: Fraunhofer-Gesellschaft zur Förderung der Angewandten Forschung e.V.

Inventor： MERZ, Peter ,  REIMER, Klaus ,  SENGER, Frank

IPC: B81C1/00

CPC classification number: B81C1/00801 ,  B81C2201/014

Abstract: The invention relates to a method for producing a micromechanical component comprising at least one self-supporting structure. According to said method a conductor track plane (11) and a sacrificial layer (4) consisting of an electrically non-conductive material are applied to a substrate (2) in such a way that the conductor track plane (11) lies between the substrate (2) and the sacrificial layer (4) or inside the sacrificial layer (4), and a layer (3) that forms the self-supporting structure is deposited on the sacrificial layer (4), the latter (4) being partially removed by etching in order to complete the self-supporting structure. An electrically conductive protective layer (15) is embedded in the sacrificial layer (4) above a region on the conductor plane (11) that is to be protected, said protective layer acting as an etching barrier during the etching process for the removal of the sacrificial layer (4). The protective layer (15) is removed again in a subsequent process, leaving a thin sacrificial layer (17) as a passivation layer lying below on the conductor tracks. The method permits sensitive areas of the conductor track plane to be protected and can be simply achieved with existing surface micromechanical processes.

公开(公告)号：EP1966822A1

公开(公告)日：2008-09-10

申请号：EP06842589.1

申请日：2006-12-18

Applicant: NXP B.V.

Inventor： SONSKY, Jan ,  VAN NOORT, Wibo, D.

IPC: H01L21/762

CPC classification number: H01L21/76229 ,  B81C1/00158 ,  B81C2201/014

Abstract: A method of manufacturing a semiconductor device wherein a laminate structure comprising a sacrificial layer is sandwiched between two etch stop layers (8,11) and which separates a semiconductor membrane (9) from a bulk substrate (1) is used to provide an underetched structure. Access trenches (4) and support trenches (5) are formed in the layered structure through the thickness of the semiconductor layer (9) and through the upper etch stop layer (8). The support trenches extend deeper through the sacrificial layer (12) and the lower etch stop layer and are filled. The sacrificial layer is exposed and etched away selectively to the etch stop layers to form a cavity (30) and realise a semiconductor membrane which is attached to the bulk substrate via a vertical support structure comprising the filled support trenches.

Abstract translation: 一种制造半导体器件的方法，其中包括牺牲层的叠层结构被夹在两个蚀刻停止层（8,11）之间并且将半导体膜（9）与体衬底（1）分开，用于提供未拉伸结构 。 通过半导体层（9）的厚度并穿过上部蚀刻停止层（8）在分层结构中形成接入沟槽（4）和支撑沟槽（5）。 支撑沟槽通过牺牲层（12）和下部蚀刻停止层更深地延伸并被填充。 牺牲层被选择性地暴露并蚀刻到蚀刻停止层以形成空腔（30）并且实现半导体膜，该半导体膜通过包括填充的支撑沟槽的垂直支撑结构附接到体衬底。

公开(公告)号：EP1880977A2

公开(公告)日：2008-01-23

申请号：EP07112635.3

申请日：2007-07-17

Applicant: Honeywell International Inc.

Inventor： Klein, Jonathan L. ,  Pilchowski, Jorg

IPC: B81C1/00

CPC classification number: B81C1/00579 ,  B81C2201/0107 ,  B81C2201/014

Abstract: Micro-electromechanical systems (MEMS) pre-fabrication products and methods for forming MEMS devices using silicon-on-metal (SOM) wafers. An embodiment of a method may include the steps of bonding a patterned SOM wafer to a cover wafer (46), thinning the handle layer of the SOM wafer (48), selectively removing the exposed metal layer (50), and either continuing with final metallization (64) or cover bonding to the back of the active layer (62).

Abstract translation: 微机电系统（MEMS）预制产品和使用硅金属（SOM）晶片形成MEMS器件的方法。 方法的实施例可以包括以下步骤：将图案化SOM晶片结合到覆盖晶片（46），使SOM晶片（48）的手柄层变薄，选择性地去除暴露的金属层（50），并且继续最终 金属化（64）或覆盖结合到有源层（62）的背面。

公开(公告)号：EP1655610A3

公开(公告)日：2007-12-19

申请号：EP06001026.1

申请日：2000-04-14

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Oguchi, Takahiro, (A170) Intell. Property Dept.

IPC: G01P15/08

CPC classification number: G01C19/5719 ,  B81B2201/025 ,  B81C1/00579 ,  B81C1/00587 ,  B81C2201/0132 ,  B81C2201/014 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  Y10S148/012 ,  Y10S148/135 ,  Y10S148/159

Abstract: A method of manufacturing an external force detection sensor in which a sensor element is formed by through-hole (20) dry etching of an element substrate (3), and an electrically conductive material is used as an etching stop layer (18) during the dry etching.

公开(公告)号：EP1180494B1

公开(公告)日：2007-01-03

申请号：EP01306284.9

申请日：2001-07-20

Applicant: Agere Systems, Inc.

Inventor： Chan, Edward ,  Kim, Jungsang ,  Huggins, Harold Alexis ,  Soh, Hyongsok

IPC: B81B3/00 ,  H03H9/17 ,  H03H3/02

CPC classification number: H03H9/173 ,  B81B2201/0271 ,  B81C1/00142 ,  B81C2201/014 ,  H03H3/02 ,  H03H2003/021

Abstract: A new bulk resonator may be fabricated by a process that is readily incorporated in the traditional fabrication techniques used in the fabrication of monolithic integrated circuits on a wafer. The resonator is decoupled from the wafer by a cavity etched under the resonator using selective etching through front openings (vias) in a resonator membrane. In a typical structure the resonator is formed over a silicon wafer by first forming a first electrode, coating a piezoelectric layer over both the electrode and the wafer surface and forming a second electrode opposite the first on the surface of the piezoelectric layer. After this structure is complete, a number of vias are etched in the piezoelectric layer exposing the surface under the piezoelectric layer to a selective etching process that selectively attacks the surface below the piezoelectric layer creating a cavity under the resonator.

公开(公告)号：EP1428255A4

公开(公告)日：2005-09-21

申请号：EP02798102

申请日：2002-08-29

Applicant: SILICON LIGHT MACHINES INC

Inventor： BRUNER MIKE

IPC: B81C1/00 ,  B81B3/00 ,  B81B7/00 ,  H01L21/46 ,  H02N1/00 ,  H03H9/24

CPC classification number: B81C1/00484 ,  B81B2201/0271 ,  B81B2203/0136 ,  B81C1/00246 ,  B81C1/00333 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2203/0136 ,  B81C2203/0735

Abstract: The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. The multi-layer structure has a capping layer (211) that preferably comprises silicon oxide and/or silicon nitride and which is formed over an etch resistant substrate (203). A patterned device layer (206), preferably comprising silicon nitride, is embedded in a sacrificial material (205, 209), preferably comprising polysilicon, and is disposed between the etch resistant substrate (203) and the capping layer (211). Access trenches or holes (219) are formed into the capping layer (211) and the sacrificial material (205, 209) is selectively etched through the access trenches (219) such that portions of the device layer (206) are released from the sacrificial material (205, 209). The etchant preferably comprises a noble gas fluoride NgF2x (wherein Ng = Xe, Kr or Ar: and where x = 1, 2 or 3). After etching that sacrificial material (205, 209), the access trenches (219) are sealed to encapsulate (241) released portions the device layer (206) between the etch resistant substrate (203) and the capping layer (211). The current invention is particularly useful for fabricating MEMs devices, multiple cavity devices and devices with multiple release features.

公开(公告)号：EP1344746A2

公开(公告)日：2003-09-17

申请号：EP03251321.0

申请日：2003-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Lee, Eun-sung ,  Kim, Chung-woo ,  Song, In-sang ,  Kim, Jong-seok ,  Lee, Moon-chul

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81B3/0078 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2203/04 ,  B81C2201/0107 ,  B81C2201/014 ,  H01H59/0009

Abstract: A method for fabricating a MEMS device having a fixing part, driving part, electrode part, and contact parts on a substrate. A driving electrode is formed on the substrate, and then an insulation layer is formed thereon. The insulation layer is patterned, and the regions of the insulation layer in which the fixing part and the contact parts are formed are etched. A metal layer is formed on the substrate. The metal layer is planarized down to the insulation layer, and the driving electrode is formed. A sacrificial layer is formed on the substrate, and a groove-shaped space is formed in a region in which the fixing part is formed. A MEMS structure layer is formed on the sacrificial layer. Sidewalls are formed in the groove-shaped space, and the fixing part and driving part are formed, leaving the sacrificial layer underneath the fixing part.

Abstract translation: 一种用于制造在基板上具有固定部分，驱动部分，电极部分和接触部分的MEMS器件的方法。 在基板上形成驱动电极，然后在其上形成绝缘层。 对绝缘层进行图案化，并且蚀刻形成有固定部和接触部的绝缘层的区域。 在基板上形成金属层。 金属层被平坦化到绝缘层，并且形成驱动电极。 在基板上形成牺牲层，在形成固定部的区域形成有槽状的空间。 在牺牲层上形成MEMS结构层。 侧壁形成在槽形空间中，并且形成固定部分和驱动部分，在牺牲层之下留下固定部分。

公开(公告)号：EP3062918A1

公开(公告)日：2016-09-07

申请号：EP13896392.1

申请日：2013-10-30

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： MCKAY, Roger A. ,  SADIK, Patrick W.

IPC: B01D69/00

CPC classification number: B81C1/00539 ,  B81B2201/058 ,  B81C1/00119 ,  B81C2201/0115 ,  B81C2201/014 ,  C23C14/5873 ,  C23F1/02 ,  C23F1/16 ,  H01M4/0492 ,  H01M4/386

Abstract: Etching islands are formed on a first face of a substrate and a second face of the substrate non-parallel to the first face. The first face and the second face of the substrate are concurrently exposed to a solution that reacts with the etching islands to concurrently form porous regions extending into the first face and the second face.

Abstract translation: 蚀刻岛形成在基板的第一面和不平行于第一面的基板的第二面上。 衬底的第一面和第二面同时暴露于与蚀刻岛反应的溶液，以同时形成延伸到第一面和第二面的多孔区域。