公开(公告)号：EP1546217A1

公开(公告)日：2005-06-29

申请号：EP03753288.4

申请日：2003-09-09

申请人： Infineon Technologies AG

发明人： SCHMID, Günter ,  KLAUK, Hagen ,  HALIK, Marcus ,  ENGL, Reimund ,  WALTER, Andreas

IPC分类号： C08F8/02 ,  H01L51/30

CPC分类号： C08F8/02 ,  H01L27/28 ,  H01L51/004

摘要： The invention relates to polymers displaying a resistive hysteresis effect. The polymers comprise a polymer backbone onto which lateral pentaarylcyclopentadienyl groups are bonded. A resistive memory element may be produced by means of the polymer, which contains the polymer as storage medium. By application of a voltage, the memory element may be switched from a non-conducting to a conducting state.

公开(公告)号：EP1540421A1

公开(公告)日：2005-06-15

申请号：EP03798060.4

申请日：2003-09-03

申请人： Infineon Technologies AG

发明人： KIRCH, Oliver

IPC分类号： G03F7/004 ,  G03F7/039 ,  G03F7/40

CPC分类号： G03F7/0045 ,  G03F7/0392 ,  G03F7/405

摘要： The invention relates to a photoresist, in addition to a method for structuring substrates, which uses the inventive photoresist. Said photoresist contains triphenylsulfonium perfluoroalkane sulfonate as the photo-acid and triphenylsulfonium acetate as the photo-base. The photoresist exhibits an extremely high exposure sensitivity and is thus ideally suited to electron beam lithography. A resolution of less than 90 nm can thus be achieved for a sensitivity of

公开(公告)号：EP1532851A1

公开(公告)日：2005-05-25

申请号：EP03790746.6

申请日：2003-08-25

申请人： Infineon Technologies AG

发明人： ZSCHIESCHANG, Ute ,  HALIK, Marcus ,  KLAUK, Hagen ,  SCHMID, Günter

IPC分类号： H05K3/12 ,  H05K1/09 ,  H01L51/20 ,  H01L51/40

CPC分类号： H05K3/207 ,  H01L51/0021 ,  H01L51/0022 ,  H01L51/0512 ,  H01L51/0541 ,  H05K3/1275 ,  H05K2201/0133 ,  H05K2201/0329 ,  H05K2203/0113

摘要： The invention relates to the production of a conductive organic track on a substrate. The inventive method consists in charging a printer buffer provided with a structured hydrophobe printing surface with a printing solution which contains a conductive organic polymer, and in forming a structured organic polymeric layer on said substrate by contacting a hydrophilic support. Said method can be continuously used by selecting appropriated geometrical characteristics for the printer buffer and substrate.

公开(公告)号：EP0953986A3

公开(公告)日：2005-05-11

申请号：EP99105689.6

申请日：1999-03-19

申请人： Infineon Technologies AG

发明人： Haerle, Dieter ,  Heyne, Patrick ,  Buck, Martin

IPC分类号： G11C29/00

CPC分类号： G11C29/006 ,  G11C29/26 ,  G11C29/48 ,  G11C29/56

摘要： Die Erfindung betrifft eine Anordnung zum Testen mehrerer Speicherchips (1) auf einem Wafer, bei der unter Verwendung von Nadeln (6) den Speicherchips (1) Versorgungsspannungen (VDD, VSS), ein Initialisierungssignal (I), ein Auslesesignal (CS), ein Taktsignal (CLK) sowie Adressen-, Daten- und Steuersignale zugeführt sind. Die Adressen-, Daten- und Steuersignale werden dabei von einer im Kerf (2) des Speicherchips angeordneten Logik (5) erzeugt und den Speicherchips (1) direkt zugeführt.

公开(公告)号：EP1495470A1

公开(公告)日：2005-01-12

申请号：EP03722511.7

申请日：2003-04-17

申请人： Infineon Technologies AG

发明人： LEUSCHNER, Rainer ,  STOJAKOVIC, George ,  NING, Xian, J.

IPC分类号： G11C11/15 ,  G11C11/16

CPC分类号： H01L27/228 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/16 ,  H01F41/308 ,  H01L43/12

摘要： A resistive memory device (110) and method of manufacturing thereof comprising a cap layer (140) and hard mask layer (142) disposed over magnetic stacks (114), wherein either the cap layer (140) or hard mask layer (142) comprise WN. A seed layer (136) disposed beneath the magnetic stacks (114) may also be comprised of WN. The use of the material WN improves etch process selectivity during the manufacturing process.

摘要翻译： 一种电阻式存储器器件及其制造方法，包括设置在磁性堆叠（114）上方的盖层（140）和硬掩模层（142），其中盖层（140）或硬掩模层（142）包括 WN。 设置在磁性叠层（114）下方的种子层（136）也可以由WN构成。 材料WN的使用提高了制造过程中的蚀刻工艺选择性。

公开(公告)号：EP1476880A2

公开(公告)日：2004-11-17

申请号：EP03742532.9

申请日：2003-02-18

申请人： Infineon Technologies AG

发明人： HOENIGSCHMID, Heinz ,  VIEHMANN,Hans-Heinrich

IPC分类号： G11C29/00

CPC分类号： G11C11/16 ,  G11C17/14 ,  G11C29/72 ,  G11C29/789

摘要： It is difficult to fabricate a semiconductor memory device without any faulty memory storage cells. One solution is to produce more storage cells than needed on a device and faulty storage cells are replaced by the redundant storage cells. This solution requires that the addresses of the faulty storage cells, along with the replacement storage cells, be saved in a memory. The present invention teaches the use of non-volatile memory cells, particularly magnetoresistive random access memory (MRAM) cells, to store the addresses. Non-volatile memory cells can effectively replace the laser fuses currently used and also provides an advantage in the elimination of the laser fuse-burning step during the fabrication of the device.

公开(公告)号：EP1466330A2

公开(公告)日：2004-10-13

申请号：EP03702435.3

申请日：2003-01-14

申请人： Infineon Technologies AG

发明人： RABERG, Wolfgang

IPC分类号： G11C11/16

CPC分类号： G11C11/16

摘要： A resistive memory element (144), magnetic random access memory (MRAM) device, and methods of manufacturing thereof, wherein a thin oxide layer (132) is disposed within the first metal layer (136) of thememory element (144). The thin oxide layer (132) comprises an oxygen mono-layer. The roughness of subsequently-formed layers (134/118/116) is reduced, and magnetic capabilities of the resistive memory element (144) are enhanced by the use of the thin oxide layer (132) within the first metal layer (136).

公开(公告)号：EP1371093A2

公开(公告)日：2003-12-17

申请号：EP02727262.4

申请日：2002-03-22

申请人： Infineon Technologies AG

发明人： KASKO, Igor ,  KROENKE, Matthias

IPC分类号： H01L21/8246 ,  H01L21/02

CPC分类号： H01L21/76855 ,  H01L21/7687 ,  H01L21/76888 ,  H01L28/55 ,  H01L28/75

摘要： The invention relates to a method for producing ferroelectric memory cells in accordance with the stack principle. According to said method, an adhesive layer (2, 3) is formed between a lower capacitor electrode (6) of a memory capacitor and a conductive plug (1), which is formed below said electrode and makes an electric connection between said capacitor electrode (6) and a transistor electrode of a selection transistor that is formed in or on a semiconductor wafer. An oxygen diffusion barrier (4, 5) is formed above the adhesive layer and once the ferroelectric has been deposited, the adhesive layer and the barrier are subjected to rapid thermal processing (RTP) in an oxygen atmosphere. The method is characterised by the following steps: (A) Determination of the oxygen speed of the adhesive layer (2, 3) and the diffusion coefficient (DOxygen(T)) of oxygen in the material of the adhesive layer (2, 3), dependent on the temperature (T); (B) Determination of the diffusion coefficient (DSilicon(T)) of silicon in the material of the adhesive layer (2, 3), dependent on the temperature and (C) Calculation of an optimal temperature range for the RTP step from the two diffusion coefficients, (DOxygen(T)) and (DSilicon(T)) that have been determined for a predetermined layer thickness (dBARR) and layer width (bBARR) of the layer system consisting of the adhesive layer and the oxygen diffusion barrier, so that during the RTP step the siliconisation of the adhesive layer occurs more rapidly than its oxidation.

公开(公告)号：EP1342243A2

公开(公告)日：2003-09-10

申请号：EP01270888.9

申请日：2001-12-03

申请人： Infineon Technologies AG

发明人： HOENIGSCHMID, Heinz ,  MUELLER, Gerhard

IPC分类号： G11C11/22 ,  H01L27/115

CPC分类号： G11C11/22

摘要： The aim of the invention is to guarantee a high degree of flexibility and a compact construction. To this end, the existing plate conduction device (50) of a memory device (1) which functions on the basis of a hysteresis process is configured to detect the state of a memory capacitor (10) and hence, the information that is stored.

公开(公告)号：EP1340230A2

公开(公告)日：2003-09-03

申请号：EP01999944.0

申请日：2001-11-22

申请人： Infineon Technologies AG

发明人： THEWES, Roland ,  WEBER, Werner ,  VAN DEN BERG, Hugo

IPC分类号： G11C11/15

CPC分类号： G11C11/15 ,  G11C11/16

摘要： The invention relates to a magnetoresistive memory and is characterized by a control circuit (1) with a first pole which, via a reading distributor (14), can be individually connected to first ends of bit lines (4a, 4b) by means of switching elements (8a, 8b). Said control circuit also has a second pole, which supplies power to an evaluator (2), and has a third pole that is connected to a reference voltage source (U5). The readout circuit additionally comprises a third voltage source (U3) having a voltage, which is approximately equal to the voltage of the first reading voltage source (U1) and which can be individually connected to second ends of the bit lines (4a, 4b) by means of switching elements (9a, 9b). Finally, the readout circuit comprises a fourth voltage source (U4), which can be individually connected to second ends of the word lines (5a, 5b) by means of switching elements (7a, 7b).