摘要:
Provided is a device identifying method for identifying an electronic device including an actual operation circuit operating at a time of actual operation of the electronic device and a test circuit provided with a plurality of test elements and operating at a time of testing of the electronic device, the device identifying method including: a property measuring step of measuring electric properties respectively of the plurality of test elements; an identification information storing step of storing the electric properties respectively of the plurality of test elements, as identification information of the electronic device; an identification information obtaining step of measuring, in an attempt to identify a target electronic device, electronic properties of a plurality of test elements included in the target electronic device, thereby obtaining identification information of the target electronic device; and a matching step of comparing the identification information obtained in the identification information obtaining step and the identification information stored in the identification information storing step, and judging that, when there is matching in identification information, the target electronic device whose identification information is obtained in the identification information obtaining step is the electronic device whose identification information is stored in the identification information storing step.
摘要:
To provide a cell or tissue embedding device highly capable of supplying a physiologically active substance, by curbing the reduction of living cells or living tissue in the process of preparing a PVA gel containing the living cells or living tissue. An aqueous gel to form an immunoisolation layer of a cell or tissue embedding device has, as its component, a polyvinyl alcohol resin having a syndiotacticity of 32 to 40% in triad.
摘要:
The present invention concerns a CMOS semiconductor device comprising at least a pair of n-channel transistor (100n) and a p-channel transistor (100p), in which each of said n-channel and said p-channel transistors is comprised of a channel region, a source region (17,18) formed at one of both sides of said channel region, a drain region (17,18) formed at another one of the both sides of said channel region, two first electrodes (21,22) electrically connected to said source and said drain regions (531,532), respectively, and a second electrode (16) formed on said channel region through a gate insulating film (15), the interface between said channel region and said gate insulating film (15) is made flat at the atomic level, at least contact portions of said first electrodes respectively contacting the source and the drain regions (17) of said n-channel transistor (100n) are formed of a first metal silicide, at least contact portions of said second electrodes respectively contacting the source and the drain regions (18) of said p-channel transistor (100p) are formed of a second metal silicide different from said first metal silicide, and said CMOS semiconductor device is an accumulation-mode transistor.
摘要:
A semiconductor device manufacturing method includes the steps of ion-implanting a p-type or an n-type impurity into a Si layer portion to become a p-type or an n-type contact region of a semiconductor device, forming a metal film for a contact on a surface of the contact region without performing heat treatment for activating implanted ions after the ion-implanting step, and forming a silicide of a metal of the metal film by causing the metal to react with the Si layer portion by heating. It is desired to simultaneously perform the step of forming the silicide and the step of activating the implanted ions by heat treatment after the metal film is formed.
摘要:
In a semiconductor device according to the present invention, an insulator layer on a substrate is provided with a trench. A gate electrode is formed in the trench so that an upper surface of the gate electrode is approximately flush with an upper surface of the insulator layer. On the gate electrode, a semiconductor layer is provided via a gate insulating film. At least one of a source electrode and a drain electrode is electrically connected to the semiconductor layer. Particularly, the gate insulating film includes an insulator coating film provided on the gate electrode, and an insulator CVD film formed on the insulator coating film.
摘要:
An accumulation mode transistor has an impurity concentration of a semiconductor layer in a channel region at a value higher than 2×10 17 cm -3 to achieve a large gate voltage swing.
摘要翻译:累积模式晶体管的沟道区中的半导体层的杂质浓度高于2×10 17 cm -3,以实现大的栅极电压摆动。
摘要:
A transistor capable of adjusting a threshold value is obtained by adjusting an impurity concentration of a silicon substrate supporting an SOI layer and by controlling a thickness of a buried insulating layer formed on a surface of the silicon substrate in contact with the SOI layer.
摘要:
Granular calcium oxide and calcium hydroxide which are highly reactive with a halide gas and its decomposition products and favorably employable for filling a gas-fixing unit (32) of an apparatus (3) for fixing a halide gas are, respectively, a granule of porous spherical calcium oxide particles, which has a BET specific surface area of 50 m 2 /g or more and a total pore volume of pores having a diameter of 2-100 nm in the range of 0.40-0.70 mL/g and a granule of porous spherical calcium hydroxide particles which has a BET specific surface area of 20 m 2 /g or more and a total pore volume of pores having a diameter of 2-100 nm in the range of 0.25-0.40 mL/g.
摘要:
The present invention makes it possible for a flow rate to be controlled to be switched easily by means of an orifice being changed conveniently without disassembling or assembling a pressure type flow rate control apparatus. An orifice changeable pressure type flow rate control apparatus of the present invention is so constituted that a valve body (23) of a control valve (2) for a pressure type flow rate control apparatus (A) is installed between an inlet side fitting block (39) provided with a coupling part of a fluid supply pipe and an outlet side fitting block (43) provided with a coupling part of a fluid takeout pipe; a fluid inlet side of the valve body (23) and the afore-mentioned inlet side fitting block (39), and also a fluid outlet side of the afore-mentioned valve body (23) and the afore-mentioned outlet side fitting block (43) are detachably and hermitically connected, respectively, so that a flow passage for gases through the afore-mentioned control valve (2) is formed; and, a gasket type orifice (38) for a pressure type flow rate control apparatus (A) is removably inserted between a gasket type orifice insertion hole (42c) provided on the outlet side of the afore-mentioned valve body (23) and a gasket type orifice insertion hole (43b) of the outlet side fitting block (43b).
摘要:
Disclosed is a shower plate which is formed with a large number of process-gas blowing holes having a simple structure, high machinability and high dimensional accuracy without the risk of unevenness in blowing of a process gas and outbreak of particles, while ensuring constant quality and interchangeability. Through a press forming process, a powder for a ceramic material with a low dielectric constant is formed into a disc-shaped compact having dimensions determined in consideration of a sintering shrinkage value and a machining value. A gas inlet passage 3 and a large number of blowing holes 2 for a compact stage are bored in the disc-shaped compact, and then the disc-shaped compact is sintered. Subsequently, the gas inlet passage 3 and a main hole portion 2b in each of the blowing holes are subjected to grinding to have a surface roughness of 1 s or less. Further, a lapping wire having a taper-shaped end is inserted into an outlet port 2a of the blowing hole 2, and reciprocatingly moved while being slidingly displaced in such a manner that a portion of the lapping wire located in the outlet port 2a is gradually increased in wire diameter, so that the outlet port 2a is lapped to have a diameter of from 0.1 mm to less than 0.3 mm, a dimensional accuracy within ± 0.002 mm, and a surface roughness of 1 s or less.